Mips Technologies, Inc.

Bruce J Ableidinger

Ernest Lewis Edgar

A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.

Apparatus and method for profiling software performance on a processor with non-unique virtual addresses

A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.

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Portland, OR, United States of America

Bruce J Ableidinger