Unisys Corporation

Bruce Howard Williams

Glenn A Arbanas

Roy E Greeff

David William Matolak

Thomas Robert Giallorenzi

Johnny Michael Harris

Robert William Steagall

A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

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Salt Lake City, UT, United States of America

Bruce Howard Williams