Nvidia Corporation

Teralogic, Inc.

Infineon Technologies North America Corp.

Zoran Corporation

Siemens Aktiengesellschaft

Csr Technology Inc.

Bruce Holmer

David R Auld

Gerard K Yeh

Hong-Jyeh Jason Huang

Rod G Fleck

Roger D Arnold

Guillermo Juan Rozas

Edward Anthony Hutchins

Alexander Klaiber

Darrell D Boggs

Paul S Serris

Vojin G Oklobdzija

Ross Segelken

Magnus Ekman

James Van Zoeren

Balraj Singh

Eric John Chesters

Hens Vanderschoot

Brad Hoyt

Sridharan Ramakrishnan

Peter Trajmar

Joseph Cesana

Danielle G Lemay

James T Battle

Anoush Khazeni

Meng-Day Yu

Hank Guo

Edward Wang

Steve Chiou

Ole H M&oslash;ller

Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.

Managing potentially invalid results during runahead

According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

Interactive set-top box having a unified memory architecture

A method and system for accessing texture data is disclosed. The method includes the step of storing a low resolution version of a block of texture data in a low latency memory and storing a high resolution version of the block of texture data in high latency memory. Upon a request for the high resolution version of the block of texture data, the high resolution version is fetched from the high latency memory to the low latency memory. The low resolution version is subsequently accessed from the low latency memory until the high resolution version is fetched into the low latency memory.

Method and system for a texture-aware virtual memory subsystem

A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be processed using 'lower-precision' units with power efficient circuitry without any quality and performance sacrifice (e.g., realism, resolution, etc.). By classifying the primitives and selecting the more power-efficient processing unit to process the primitive, power consumption can be reduced without quality and performance sacrifice.

High quality and high performance three-dimensional graphics architecture for portable handheld devices

A method and apparatus for display of graphical data is described. The invention provides an architecture for graphics processing. The architecture includes pipelined processing and support for multi-regional graphics. In one embodiment, a graphics driver according to the invention can receive multiple independent streams of graphical data that can be in different graphical formats. The independent streams are synchronized and converted to a common format prior to being processed. In one embodiment, multi-regional graphics are supported with off-screen and on-screen memory regions for processing. The regions of the multi-regional graphic are rendered in an off-screen memory. The data in the off-screen memory are converted to a common format and copied to on-screen memory. The data in the on-screen memory is used to generate an output image. Alpha blending can also be programmed to provide multi-regional graphics or other graphical features. In one embodiment, graphics processing is programmable and can be paced using a set of registers.

Graphics engine architecture

An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.

Data processing unit with interface for sharing registers by a processor and a coprocessor

The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.

Aspect ratio correction using digital filtering

An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each instruction contains at least a single bit indicating said instruction sizes. An instruction buffer coupled with an instruction size evaluation unit for determining the instruction size upon said at least single bit of said instruction is provided.

Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively

The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save area. The memory is coupled with the register file and an instruction control unit with a program counter register and a program status word register coupled with the memory and the register file. The method comprises the steps of acquiring a new save area from said unused save area, storing the context of the first task in said new area, linking the new area with said previous context save area.

Data processing unit with hardware assisted context switching capability

Growing community of inventors

Belmont, CA, United States of America

Bruce Holmer