Unisys Corporation

Bruce H Williams

Glenn A Arbanas

Roy E Greeff

Valjean P Snyder

Christopher R Keate

Patrick S Grant

Jeffrey Mac Thornock

Thomas R Giallorenzi

Johnny M Harris

Robert W Steagall

David William Matolak

Mark B Falslev

Rov E Greeff

An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated by amplifying the input signal with one particular gain when the input signal is at a maximum magnitude which gives the distorted output signal a corresponding maximum magnitude, and by amplifying the input signal with a larger gain when the input signal is in a predetermined range below the maximum magnitude. The distorted output signal travels over a communication channel to a receiver circuit, which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.

Data transmisson system with a low peak-to-average power ratio based on

An improved quadrature phase shift key modulator circuit of the type which includes a non-linear amplifier in the transmitter and includes a frequency select logic circuit for receiving the in phase and quadrature phase digital data to be modulated onto a carrier frequency signal. The output of the frequency select circuit produces select signals that are coupled to the input of a digital carrier frequency generator. The digital carrier frequency generator synthesizes and increases, decreases, or leaves unchanged the carrier frequency as a representation of the data occurring on the in phase and quadrature phase input lines. The output of the digital carrier frequency generator is smoothed and converted to an analog signal which has a constant vector power magnitude during phase change. The constant vector power when amplified in a non-linear amplifier of the transmitter is not susceptible to regeneration of side lobes of the carrier signal, thus, provides a more narrow bandwidth modulated carrier frequency signal.

Offset quadrature phase shift keyed modulation circuit

An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.

Phase lock indicator circuit for a high frequency recovery loop

An improved digital data modulator is provided for a digital transmitter. The digital data modulator comprises of a pair of digital data synthesizers which are controlled in a manner which produces complex conjugate modulated data signals of the input signals. Summing means are provided to sum the outputs of the digital data synthesizers in a manner which removes the imaginary components and simultaneously reduces the side load power without employing conventional filters.

BPSK modulator for a digital signal transmitter

A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Digitally implemented phase and lock indicators for a bit synchronizer

A dual loop phase locked circuit is disclosed in which a first loop includes a phase detector, a filter, and a VCO; as a second loop includes a sweep voltage generator, a compensation circuit, and the filter of the first loop. Due to the compensation circuit, the VCO accurately tracks a signal from the sweep voltage generator, even though the filter has an electrical parameter that drifts with time and/or age and/or component selection.

Dual loop phase locked circuit with sweep generator and compensation for

Embodiments disclose an adjustable filter (cf voltage-controlled bandwidth) having photoconductors whose resistance is adjusted by variable-intensity radiation source means, with a related feedback loop to compensate for thermal changes.

Radiation-controlled filter with photoconductor means and feedback

Adjustable radiation-controlled filter with voltage controlled bandwidth

Self-clocking system for demodulating phase encoded data automatically tracks incoming data rate changes by using information from a bit synchronizer to track the incoming base band data signal.

Self-clocking system

Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency. The automatic frequency control circuit is adapted to drive the output of the voltage controlled oscillator to the center frequency of the doppler shifted carrier frequency without overshoot and then enable the phase lock loop to phase lock onto the phase of the doppler shifted carrier frequency to provide a locked on condition.

Smart sweep apparatus for data rate receivers

The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

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Sandy, UT, United States of America

Bruce H Williams