Applied Micro Circuits Corporation

Daylight Solutions, Inc.

Bruce H Coy

Hongming An

Shyang Kye Kong

Miles James Weida

Kenneth Smetana

David S Rosky

David F Arnone

William Chapman

Raymond C Yuen

Brian Lee Abernathy

Brian Abernethy

Paul Edward Vanderbilt

A laser assembly () for generating a pulsed output beam () includes a quantum cascade device (); and a laser driver (A) that controls the voltage to the quantum cascade device () in a pulsed drive profile () to generate the pulsed output beam (). The pulsed drive profile () includes a plurality of spaced on-time segments () in which the laser driver (A) directs voltage to the quantum cascade device (), and at least one off-time segment () in which the laser driver (A) pulls down the voltage from the quantum cascade device (). The off-time segment () occurs between two on-time segments ().

Pulsed quantum cascade device assembly with active voltage pulldown

A chromatography analyzer system () for analyzing a sample () includes a MIR analyzer () for spectrally analyzing a sample fraction (A) while the sample fraction (A) is flowing in the MIR analyzer (). The MIR analyzer () includes (i) a MIR flow cell (C) that receives the flowing sample fraction (A), (ii) a MIR laser source (A) that directs a MIR beam (B) in a MIR wavelength range at the sample fraction (A) in the MIR flow cell (C), and (iii) a MIR detector (D) that receives light from the sample fraction (A) in the MIR flow cell (C) and generates MIR data of the sample fraction (A) for a portion of the MIR wavelength range.

Liquid chromatography analyzer system with on-line analysis of eluting fractions

An assembly () for analyzing a sample () includes a detector assembly (); a tunable laser assembly (); and (iii) a laser controller (F). The detector assembly () has a linear response range () with an upper bound (A) and a lower bound (B). The tunable laser assembly () is tunable over a tunable range, and includes a gain medium (B) that generates an illumination beam () that is directed at the detector assembly (). The laser controller (F) dynamically adjusts a laser drive to the gain medium (B) so that the illumination beam () has a substantially constant optical power at the detector assembly () while the tunable laser assembly () is tuned over at least a portion of the tunable range.

Laser power adjustment during tuning to compensate for detector response and varying background absorption

A system and method are provided for adjusting the phase output of a Hogge phase detector. The method comprises: using a Hogge phase detector, generating a reference signal; using the Hogge phase detector, generating a phase and reference signals; accepting an adjust signal; modifying the amplitude of the phase signal in response to the adjust signal; integrating the amplitude modified phase signal; using the integrated signal as a phase adjusted signal; integrating the reference signal; using the integrated reference signal and phase adjusted signal to generate a voltage controlled oscillator (VCO) signal; at the Hogge phase detector, accepting the VCO signal as the clock signal. Some aspects of the method further comprise: using the VCO signal to sample data at a settled first phase of the clock; changing the adjust signal; and, using the VCO signal to sample data at a settled second phase of the clock.

Hogge phase detector with adjustable phase output

A system and method are provided for measuring amplifier gain in a digital network. The method includes accepting a digital input signal; amplifying the input signal (Vin); comparing the amplified signal to dc thresholds; measuring output errors; and, calculating the amplifier gain in response to the thresholds. More specifically, accepting a digital input signal includes accepting an input signal having an amplitude. Comparing the amplified signal to dc thresholds includes comparing the amplified signal to a low threshold and a high threshold. Measuring errors includes measuring a predetermined error condition in response to the high threshold and the low threshold. Then, calculating the amplifier gain in response to the thresholds includes calculating the amplifier gain in response to the high threshold, the low threshold, and the input signal amplitude.

System and method for measuring amplifier gain in a digital network

A system and method are provided for compensating a comparator threshold level. The method comprises: accepting an input signal with an ac component; lowpass filtering the input signal to generate the input signal average voltage; accepting the input signal average voltage; accepting a first dc level; summing the average voltage with the first dc level; supplying a first sum as a first comparator threshold level; comparing the input signal to the first comparator threshold level; and, supplying a first comparator output signal with an ac component. In some aspects of the method, accepting a first dc level includes accepting a plurality of dc levels. Then, the average voltage is summed with each of the plurality of dc levels and supplied as a corresponding plurality of comparator threshold levels. The input signal is compared to each of the comparator threshold levels and a plurality of comparator output signals are supplied.

System and method for comparator threshold adjustment

A system and method are provided for controlling the phase of a voltage controlled oscillator output. The method comprises: accepting a plurality of VCO outputs coarsely differentiated by phase; selecting one of the VCO outputs; finely modifying the phase of the selected VCO output; and, supplying the phase modified VCO output. In one aspect, accepting VCO outputs coarsely differentiated by phase includes: accepting a first VCO output (I ); accepting a second VCO output (I ), differentiated approximately 90 degrees from the first VCO output; accepting a third VCO output (Q ), differentiated approximately 90 degrees from the second VCO output; and, accepting a fourth VCO output (Q ), differentiated approximately 90 degrees from the third VCO output. Finely modifying the phase of the selected VCO output includes modifying the selected VCO output in the range between &plus;45 and &minus;45 degrees. In one aspect, the output is modified in 16 discrete steps.

System and method for voltage controlled oscillator phase interpolation

A dual loop system for the acquisition and tracking of a carrier signal is presented. The acquisition loop uses a bang-bang phase detector which permits the carrier to be acquired without a clock reference. Once acquired, the carrier is then tracked with a loop using a Hogge phase detector. The tracking loop is autoscaling, so that loop gain and bandwidth are responsive to the carrier signal frequency. The autoscaling feature of the tracking loop and the uniform gain of the acquisition loop permit the same loop filter to be shared by both loops. A method implementing the above-described dual-loop system is also presented.

Dual-loop system and method for frequency acquisition and tracking

A system and method are provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The comparator system comprises amplification stages with bias cancellation circuitry and a threshold setting circuit. The bias offset current cancellation circuit is used to cancel the base current of differential amplifier input emitter follower. The bias offset current cancellation circuit also cancels the loading effect of amplifier input emitter-follower driving stage. The threshold offset voltage is further reduced by the threshold setting circuit. The threshold-setting circuit includes two integrators and a unit gain operation amplifier. The integrators have the input accept a single-ended input signal, an output connected to the negative input of the comparator, and an output connected to the unit gain operational amplifier, whose output is connected to the negative input of the comparator.

System and method for threshold bias offset voltage cancellation in a comparator

An integrated circuit device and method for synthesis of a signal having a desired frequency and low noise. The integrated circuit embodiment of the invention generally includes a phase locked loop (PLL) circuit used in conjunction with a frequency multiplier. Specifically, the integrated circuit embodiment includes a frequency multiplier connected to a first input of a phase detector, a low pass filter connected between the output of the phase detector and the input of a voltage controlled oscillator (VCO), and a frequency divider connected between the output of the VCO and a second input to the phase detector. The frequency multiplier produces a signal having a frequency that is a multiple of the frequency of a reference signal which is connected to the input of the frequency multiplier. For any desired output frequency, use of the multiplier results in a smaller divider ratio 'n' in the PLL, thereby reducing the closed loop noise inside the PLL loop bandwidth. Other embodiments of the invention include a method for low noise frequency synthesis, and a method of low noise frequency synthesis for clocking data onto a SONET OC-48 channel. The invention provides the advantage of frequency synthesis with low noise.

Integrated circuit and method for low noise frequency synthesis

A ramp circuit discharges an output capacitor to generate a substantially linear ramp signal, current injection is used to stabilize the ramp's output, reducing overshooting and ringing. With faster output stabilization, the ramp exhibits significantly faster repetition rates suitable testing high speed components such as RAM, microprocessors, high speed logic, and the like. The ramp includes an output transistor, with its output defining an output node coupled to a current source and a charge storage device such as a capacitor. The charge storage device charges when the transistor is 'on'. Namely, when the transistor is turned on, the output charge storage device is coupled to a reference voltage, which charges the device in a fixed time. When the transistor is turned 'off', the charge storage device discharges, aided by the flow of current through the current source, resulting in the linear ramp signal. After the charge storage device discharges, current injection is used to quickly stabilize the ramp's output. Particularly, while the output transistor is turned on, permitting the charge storage device to recharge, a transistor couples a bias current source to the output node. Specifically, the transistor is configured to selectively couple the bias current source to the output node when the output transistor is turned on, or a predetermined time thereafter. Conversely, the transistor selectively decouples the bias current source from the output node when the ramp output arrives within a predetermined threshold value of the target ramp starting value.

Current injected ramp with reduced recovery time background of the

A timing vernier repeatedly generates a timing output signal, which includes a timing event such as a state transition, pulse, etc. Unlike prior timing verniers, the present timing event is capable of significantly faster repetition rates. After the ramp signal is initiated responsive to a trigger signal, it changes from a predetermined starting level at a predetermined substantially linear rate. A digital-to-analog converter (DAC) provides an analog timing select signal and a reset select signal responsive to a digital timing select signal. The reset select signal represents the current timing select signal offset by a predetermined amount. A comparator, coupled to the ramp and the DAC, produces the timing event when the ramp output signal reaches the analog timing select signal. Thus, greater analog timing select signals cause earlier timing events, whereas lesser timing select signals result in later timing events. The delay of the timing event is directly proportional to the analog timing select signal. A threshold sensor, coupled to the ramp and the DAC, provides the ramp's reset signal when the ramp output signal reaches the reset select signal. Since the reset select signal is automatically adjusted to be a fixed offset from the analog timing select signal, the ramp is reset as early as possible, without waiting for the ramp output signal to finish its course.

Timer with dynamic reset threshold

An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.

Analog delay circuit

A ramp circuit repeatedly generates a substantially linear ramp signal. Ramp switch junction capacitance that otherwise causes a nonlinear output is compensated to improve signal linearity and enable faster retriggering. The ramp includes an output transistor, with its output coupled to a current source and a charge storage device. The output charge storage device charges when the transistor is on. When the transistor is turned off, the output charge storage device discharges, resulting in the changing ramp signal. The output transistor inherently includes a junction capacitance, which causes a nonlinearity in the discharge of the charge storage device. This nonlinearity appears as a quick drop in the ramp signal relative to the slower rate of steady-state decrease. This nonlinearity is prevented, however, by compensating for the output transistor's junction capacitance. In one embodiment, compensation circuitry includes a compensation capacitor coupled between the ramp output and a pull-up register attached to a power supply voltage. An input stage includes two transistors, each having a power supply node, an input node, and an output node. The transistors are interconnected at their output nodes, coupled to electrical ground via a current source power supply. The power supply node of the first transistor is coupled to the node connecting the pull-up resistor and the compensation capacitor. The power supply node of the second transistor is coupled to a second pull-up register attached to the power supply. The first transistor receives a reset signal input to the ramp, whereas the second transistor receives a trigger signal that is the inverse of the reset signal.

Charge balanced ramp with improved signal linearity

A method and apparatus for providing ECL output signals to a capacitative load includes differential amplification of input signals with a first output of a differential amplifier connected for establishing a voltage level between voltage limits V.sub.cc and V.sub.ee at the output of an output driver in response to variations in the first amplifier output. A pull-down transistor has a collector connected to the output driver output, an emitter connected to the V.sub.ee voltage source, and a base coupled through a boost capacitor to the second amplifier output. A voltage clamp embracing a clamp transistor with a base connected to receive a predetermined control voltage has an emitter connected to the boost capacitor and the pull-down transistor base and a collector connected to the V.sub.cc voltage source. The clamp transistor is operated in Darlington configuration to provide a minimum discharge impedence to the base of the pull-down transistor. A recovery capacitor is connected between the clamp transistor base and the first duplifier output to speed up the clamp transistor's operation.

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San Diego, CA, United States of America

Bruce H Coy