Enhanced Memory Systems, Inc.

Bruce Grieshaber

Kenneth J Mobley

David W Bondurant

Michael Peters

David Fisch

An enhanced bus turnaround integrated circuit dynamic random access memory (&ldquo;DRAM&rdquo;) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (&ldquo;ZBT&rdquo;), or pipeline burst static random access memory (&ldquo;SRAM&rdquo;) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a &ldquo;Wait&rdquo; pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

Enhanced bus turnaround integrated circuit dynamic random access memory device

An enhanced bus turnaround integrated circuit dynamic random access memory ('DRAM') device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ('ZBT'), or pipeline burst static random access memory ('SRAM') devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a 'Wait' pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

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Colorado Spring, CO, United States of America

Bruce Grieshaber