International Business Machines Corporation

Bruce Gerard Mealey

Mark D Rogers

Randal Craig Swanberg

Michael Stephen Williams

Balaram Sinharoy

Suresh Eswara Warrier

Ravi Kumar Arimilli

Peter H Hochschild

Rama Krishna Govindaraju

Satya Prakash Sharma

Vishal Chittranjan Aslot

Andre Laurent Albot

Naresh Nayar

James Anthony Pafumi

James Bernard Moody

Anil Kalavakolanu

Brian W Hart

Michael Gerard Mall

Vani D Ramagiri

Wen-Tzer Thomas Chen, Jr

Diane Garza Flemming

William A Maron

Dean J Burdick

Jeffrey A Stuecheli

Giles R Frazier

Karthick Rajamani

Bret Ronald Olszewski

Richard Louis Arndt

Pratap Chandra Pattnaik

Eric Eugene Retter

Vaijayanthimala K Anand

John Bruce Carter

Ravi Shankar

Basu Vaidyanathan

Nikhil Hegde

Thomas Stanley Mathews

James William Van Fleet

Brian Frank Veale

Michael E Lyons

Nikhil Hedge

Nick Stilwell

Steven Mark Thurber

William Joseph Armstrong

Dirk Michel

Stuart Zachary Jacobs

Mysore Sathyanaranyana Srinivas

David Alan Hepkin

Sanket Rathi

Luke Matthew Browning

Wade Byron Ouren

Grover Herbert Neuman

Greg Robert Mewhinney

Scott Leonard Daniels

Arnold Flores

Christopher F McDonald

Nakhil Hegde

Michael T Benhase

James Stephen Fields, Jr

Geraint M North

Richard Loise Arndt

Florian Alexander Auernhammer

Robert Alan Cargnoni

Louis Bennie Capps, Jr

Larry Bert Brenner

Phani Kumar V U Ayyagari

Michael John Mayfield

Sudhir Maddali

Brian Chase Twichell

Chris Alan Schwendiman

Robert Kimberlin Foster

George John Dawkins

Adam James McNeeney

Christopher Francois

Luc Rene Smolders

Stephen Dale Linam

James Britt Partridge

Venkata N S Anumula

Vinod Kumar Boddukuri

Jeffrey Scott Peek

Joshua N Poimboeuf

Jonathan Allen Wildstrom

Walter Manfred Lipp

Casey Lee McCreary

Joerg Droste

Kerry Alan Lucas

Nicholas Stilwell

Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.

Accelerator access control

A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.

Shared and exclusive accelerator access

An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Efficient critical thread scheduling for non-privileged thread requests

Efficient critical thread scheduling for non privileged thread requests

Methods and systems for migrating a virtual machine instance between devices include one or more migration risk rules, each migration risk rule relating to a validation set having one or more validation substasks. A processor is configured to score a received migration request against one or more of the migration risk rules to generate one or more scores for the migration request, to compare each score to a respective threshold to determine if a level of risk according to the respective rule merits performing validation for the validation set, to validate the migration request by only those validation sets that correspond to the scores that exceed the respective threshold, and to trigger migration of a virtual machine to a target device in accordance with the migration request if none of the validation sets fail to validate the migration request.

Risk-appropriate validation for live operating system migration

An interface superpipe is implemented in a filesystem. A filesystem in a kernel, receives a command to open a file, the command issued in the execution of a process in an application. The file is determined to be on an interface disk. It is determined that a context does not exist for the process and, in response, an adapter queue is allocated for the process in a kernel memory and mapped into a process address space associated with the process. The context information of the process is saved in the kernel memory. The filesystem may be part of a system further comprising a processor, a storage, an interface adapter in communication with the storage and sharing a memory space with the processor, and an application in communication with the filesystem.

Transparent CAPI exploitation for legacy application

Improved techniques for memory expansion are provided. A storage volume is opened on a storage device attached to a computing system, and the storage volume is configured as extended memory. A number of hardware threads available in the computing system are determined, and a number of contexts equal to the determined number of hardware threads are generated. Each context is assigned to one of the hardware threads. It is further determined that a first hardware thread has requested a first page that has been paged to the storage volume, where the first hardware thread is assigned a first context. A synchronous input output (I/O) interface is accessed to request that the first page be moved to memory, based on the first context. While the first page is being moved to memory, a priority of the first hardware thread is reduced.

Use of capi-attached storage as extended memory

A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. An active logical partition is assigned to one of a plurality of shared processor pools, each shared processor pool having a virtual processor manager mode. A target performance metric for a workload in the active logical partition is compared to a calculated CPU utilization ratio or a calculated response time ratio. The workload in the active logical partition is dynamically moved from the assigned shared processor pool to a logical partition in another of the plurality of shared processor pools based on the target performance metric not being met in the active logical partition, and wherein the logical partition in another of the plurality of shared processor pools is configured to meet the target performance metric.

Dynamic virtual processor manager

Methods for migrating a virtual machine instance between devices include scoring a received migration request against one or more rules in a rule database to generate one or more scores for the migration request. Each rule relates to one or more respective validation sets. Each score is compared to a respective threshold. The migration request is validated by only those validation sets that correspond to the scores that exceed the respective threshold. A virtual machine is migrated to a target device in accordance with the migration request responsive to successful validation by the validation sets used.

Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

Systems, methods, and computer program products to manage an address translation in a virtually segmented memory system, with included processes comprising a process scoped segment table (STAB) consisting of segment table entries (STEs) that contain effective address segment number (ESID) to system wide unique virtual segment identifier (VSID) mappings, and creating a global kernel segment table (STAB) that itself is translated using a pinned page table entry (PTE). A switch to the global kernel STAB is initiated in response to a page fault interrupt on a process STAB PTE and a PTE reload handler invoked to reload that process STAB PTE. A switch to an original STAB is initiated in order to resume the address translation and resolve the page fault or the interrupt by an operating system executing on the processor.

Virtually addressable hardware global kernel segment table

A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request to delete a memory region, forwarding the request to an intermediate software thread, and using the intermediate software thread to perform the request as a background process. The method further includes, upon receiving a message from the intermediate software thread, returning to a system caller, while performing the request, via the intermediate software thread, continues in the background.

Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers

A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request for a pool of memory, determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The dummy memory segment is filled with one or more pages, based on the determined size of the requested pool of memory, and the dummy memory segment is deleted.

Affinity aware parallel zeroing of memory in non-uniform memory access (NUMA) servers

Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers

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Austin, TX, United States of America

Bruce Gerard Mealey