International Business Machines Corporation

Bruce George Rudolph

James David Strom

Charles Luther Johnson

Robert Russell Williams

Daniel Mark Dreps

Matthew James Paschal

Robert F Lembach

Steven Michael Douskey

Robert Lowell Kanzelman

Timothy Carl Bronson

Glen Arthur Wiedemeier

Anthony DeGroff Drumm

Dana Marie Woeste

Dennis T Cox

David LeRoy Guertin

Mark E Turner

A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Redundant clock switch

A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

Oscillator failure detection circuit

An apparatus and method for providing a gated output timing signal within a gated clock distribution tree. In accordance with the present invention, a gated clock splitter includes a timing signal input and a combinatorial logic block coupled to the timing signal input that generates a gated timing signal. A gating signal input is coupled to the combinatorial logic block for selectively enabling and disabling the output from the combinatorial logic block. A gate control circuit is coupled to the gating signal input for providing a gate signal to the combinatorial logic block, wherein the gate control circuit provides a full-cycle path for said gate signal to the gating signal input.

High-speed leaf splitter for clock gating

An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards. Producing each of the variable clock signals may involve selecting between a first delay line and a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. The circuitry is selectably operable in a slave or buffer-type clock repowering mode or an adaptive mode. The variable clock signals and the output signals may respectively comprise low voltage differential signals (LVDS) or CMOS level signals.

Multiple-mode clock distribution apparatus and method with adaptive skew compensation

A phase error detection circuit apparatus and method for detecting phase misalignment between first clock signals operating in a slow time domain and second clock signals operating in a fast time domain. A frequency divider and shift register are clocked in the slow time domain to sequentially sample all possible alignments of the first clock signals. A second shift register is clocked in the fast time domain and operates responsive to the output of the frequency divider and shift register to generate a phase alignment error signal when the phase alignment is incorrect or the frequency divider is not switching in a correct cycle. Error detection logic clocked in the slow time domain samples and optionally masks the phase error signal. State machine logic may be provided to generate an output error signal when each possible phase alignment results in a phase alignment error signal.

System and method for detecting phase errors in asics with multiple clock frequencies

A simple system and method is disclosed that provides for the identification and removal of unnecessary buffers in a logic circuit. A special pseudo-buffer is added to the library and identified as a buffer cell with zero area. In addition, a feedthrough delay rule is associated with the pseudo-buffer such that it is treated by a timing system as a wire with no delay through which all electrical properties pass. An existing repowering function will then consider the pseudo-buffer as a replacement choice when attempting to select an optimal power level. If the pseudo buffer is chosen, it can be easily removed from the circuit at some time thereafter.

Simplified buffer manipulation using standard repowering function

In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

Reducing clock skew in large-scale integrated circuits

A performance-sensing element (PSE) circuit detects the actual speed of other circuits on the same chip by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.

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Rochester, MN, United States of America

Bruce George Rudolph