International Business Machines Corporation

Other

Bruce G Hazelzet

Mark William Kellogg

Timothy Jay Dell

Kevin Charles Gower

Marc Raymond Faucher

Brian John Connolly

David J Perlman

Kent A Dramstad

Clarence Rosser Ogilvie

Paul C Stabler

Christopher P Miller

Steven Alfred Grundon

Pak-kin Mak

Kamal Emile Dimitri

David John Krolak

Dale E Pontius

Kevin W Kark

Roger A Rippens

Hehching Harry Li

Liyong Wang

Carl B Ford, Iii

Donald J Swietek

Bruce W Singer

David L Arlington

James R Mallabar

Johann Werner Nagel

Bharat J Oza

Jacqueline M Cole

Darcie J Rankin

David J Perhnan

David T Perlman

James Lewis Rogers

A Frank Weaver

A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

High reliability memory module with a fault tolerant address and command bus

An enhanced four rank enabled buffer device that includes input ports for receiving input data that includes address and command data directed to one or more of up to four ranks of memory devices. The buffer device also includes one or more buffer circuits for driving one or more of the address and command data, a plurality of chip select input lines for selecting between the up to four ranks of memory devices, and a plurality of chip select output lines for accessing the up to four ranks of memory devices. The buffer device further includes a power savings means for causing one or more of the buffer circuits to be in an inactive mode when corresponding chip select input lines are not active. The buffer device is operable to access the up to four ranks of memory devices.

High density high reliability memory module with power gating and a fault tolerant address and command bus

A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes a buffer device in communication with the circuit board for accessing up to four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, a power savings means is included for causing all or a portion of the buffer device to be in an inactive mode in response to current activity at the memory module. The memory module also includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32 K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.

Memory device with programmable receivers to improve performance

A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.

Processor memory array having memory macros for relocatable store protect keys

A high density high reliability memory module with a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes one or more buffer devices in communication with the circuit board for accessing one or more of the four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, the memory module includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

High density high reliability memory module with a fault tolerant address and command bus

A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM, and a 28 bit 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit, a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

A data processing system, and a method of operating a data processing system. The data processing system comprises a clock generator for generating a system clock signal, and a memory unit having a plurality of memory modules for storing data. The data processing system further comprises a memory controller coupled to the clock generator for receiving the system clock signal therefrom, and coupled to the memory modules for outputting memory address and control signals to said modules. The memory controller is programmable to have different clock-to-output delays, on signals from the memory controller end, based on the memory installed in the system. Preferably, the memory controller includes means for generating a series of memory address and control signals in response to receiving the system clock signal, and for outputting the memory address and control signals to the memory modules; and programmable means for determining time delays between the time the memory controller receives the system clock signal and the time the memory means outputs the memory address and control signals.

Memory interface with programable clock to output time based on wide range of receiver loads

A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.

Captured synchronous DRAM fails in a working environment

A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of. a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.

Method for making a memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket

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Essex Junction, VT, United States of America

Bruce G Hazelzet