Raytheon Company

Bruce G Armstrong

Fabio Principi

Joseph T Evans, Jr

Jeff A Bullington

Jerry W Drake

Gerard J Shaw

Jok Y Go

Stephen E Bernacki

John G Marcellino

Jay H Chun

Architectures for a ferroelectric memory which avoids the half select phenomenon and the problems associated with destructive readout. Non-destructive readout is provided by measuring current through the ferroelectric memory as a measure of its resistance. Information is stored in the ferroelectric memory element by altering its resistance through a polarizing voltage. The half select phenomenon is avoided by using isolation techniques. In various embodiments, zener diodes or bipolar junction transistors are used for isolation.

Ferroelectric memory structure

A memory cell comprising a memory region of amorphous silicon, such memory region having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical programming signal applied thereto. The memory region is disposed over a metal Schottky contact, such as platinum-silicide (PtSi), formed in a support body. A first barrier layer comprising a refractory metal such as titanium-tungsten (TiW) is disposed between the memory region and Schottky contact. A first input terminal comprising a metal strip conductor, such as aluminum, is disposed over the memory region, with a second refractory metal barrier layer being disposed between the memory region and metal strip conductor. A second input terminal is disposed within the support body. With such arrangement, the material of the Schottky contact (PtSi) is substantially prevented from migrating or diffusing into the silicon memory region upon application of the electrical programming signal between the first and second input terminals, thereby preserving the structure of the metal contact and maintaining a low reverse bias leakage current for a Schottky diode comprising such metal contact. Also, the level of the programming signal may be increased, providing more complete programming of the memory region to the second, electrically conductive state.

Programmable memory cell structure including a refractory metal barrier

A memory integrated circuit component comprises: a memory; addressing circuitry for the memory; and, power switch circuit, programmable to either: (a) electrically couple or decouple the addressing circuitry and a power supply selectively in accordance with an enable signal; or, (b) maintain the addressing circuitry electrically coupled to the power supply independent of the enable signal. With such arrangement, an integrated circuit component manufacturer avoids having to produce two separate types of non-volatile integrated circuit memories (i.e., a power switched component and a non-power switched component), but rather such manufacturer is able to fabricate a common non-volatile integrated circuit memory component which may be programmed after fabrication by either the user or the manufacturer as either a non-power switched memory component or a power switched memory component.

Power switched read-only memory

An integrated circuit memory is disclosed having a power switch circuit which, in response to an enable signal, initially addresses a plurality of rows of memory elements during an initial pre-enable condition and which subsequently places the memory in the full enable condition to allow the address signal to address only a selected one of the plurality of memory elements. During a standby mode the rows of conductors coupled to the rows of memory elements are at a relatively 'high' voltage potential charging the large capacitance between the rows of conductors and a grounded substrate on which such conductors are formed. To address a particular row conductor and hence the memory elements coupled thereto during the enable mode, such row conductor must be coupled to ground potential. With the arrangement described above, by addressing a plurality of the addressed rows of conductors during the initial pre-enable condition, the relatively 'high' voltage on the plurality of rows of conductors is coupled to ground potential thereby more effectively and more rapidly discharging the voltage on the plurality of the addressed rows of conductors to reduce the effect of the capacitance, and hence the response time, of the memory circuit to the enable signal.

Integated circuit memory

An integrated circuit memory is provided wherein an array of memory elements is addressed by a decoder circuit responding to an address signal. The decoder circuit includes a plurality of sections, each one thereof being used to address a different section of the array. A decoder section selector is provided which, in response to the addressing signal, determines the section of the array being addressed and electrically couples the one of the plurality of decoder circuit sections which is coupled to such addressed array section to a power source while electrically decoupling the remaining section of the decoder circuit from such power source. With such arrangement, only a portion of the decoder circuit is electrically coupled to the power source when addressing the array thereby reducing the power consumption of the integrated circuit memory.

Integrated circuit memory

A programmable read-only memory (PROM) circuit is provided wherein each one of a plurality of fusible links is coupled between a different row and column conductor of a matrix of row and column conductors and wherein each one of the row conductors is coupled to a corresponding one of a plurality of row driver circuits, each one having an output transistor connected to the corresponding one of the row conductors. Switch means are provided for feeding a first level of base current to the output transistors during the programming mode and for feeding a second, lower level of base current to such output transistors during the read mode.

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Belmont, CA, United States of America

Bruce G Armstrong