University of Alberta

Telecommunications Research Laboratories

Other

Telecommunication Research Laboratories

Bruce F Cockburn

Vincent Gaudet

Stephen Bates

Anthony Charles Rapley

Christian B Schlegel

Gershom Birk

Robert Hang

Hongyu Liao

Mrinal K Mandal

Jeremy S Sewall

Paul Andrew Goud

Deepak P Sarda

Duncan Elliott

Christian Schlagel

Sheryl Howard

Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder () for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.

Decoder for low-density parity-check convolutional codes

An architecture and a method are provided for decoding codewords for codes such as low density parity check (LDPC) codes. An iterative decoding algorithm such as the Belief Propagation Algorithm (BPA) is employed that attempts to correct errors in an input block of symbols via a structure containing two sets of nodes through node processing and the passing of messages between nodes. Message passing and node processing is performed in a digit-serial manner instead of a bit-parallel manner.

Method and apparatus for digit-serial communications for iterative digital processing algorithms

Compact and efficient hardware architectures for implementing lifting-based DWTs, including 1-D and 2-D versions of recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a 5-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures. The recursive and dual scan architectures can be readily extended to the N-D case.

Implementation of discrete wavelet transform using lifting steps

A method and apparatus for classifying signals into a multiplicity of signal classes which employs discriminant functions of low-complexity discriminant variables that are computed directly from the passband signal. The method can be applied to the problem of classifying voiceband data (VBD), facsimile (FAX), native binary data, and speech on a 64 Kbps digital channel. In a hybrid two stage classification system, the first stage employs linear discriminant functions to make classification decisions into a smaller number of possible preliminary signal classes. The decisions of the first stage are then refined by a second stage that uses nonlinear discriminant functions such as quadratic or pseudo-quadratic functions. The second stage of a hybrid classifier then assigns the signal into a larger number of possible classes than does the first stage of the classifier alone.

Voiceband signal classifier

A dynamic random access memory for storing one of N levels in each of a plurality of memory cells, the memory cells having storage capacitors coupled to bitline pairs through switches for writing and reading data to and from the memory cells, the memory comprising: at least N&minus;1 bitline pairs, each bitline pair being divided into N&minus;1 sub-bitlines by first switches therebetween; the sub-bitline pairs of each bitline being coupled to adjacent sub-bitline pairs by second switches therebetween, to form N&minus;1 groups of sub-bitlines each for producing one of N&minus;1 reference voltages; sense amplifiers coupled to each sub-bitline pair; N&minus;1 sub-bitline pairs each having reference cells for selective coupling thereto; (N&minus;2)(N&minus;1) sub-bitline pairs each having generate cells for selective coupling thereto; and sub-bitline pairs being selectively connected in a group through switches such that: the sub-bitlines in the group are precharged to one of a plurality of voltages; one of the (N&minus;1) reference voltages is generated by shorting together sub-bitlines in the group; and the reference voltage is stored in a reference cell in one of the bit-line pairs in the group.

System and method for multilevel DRAM sensing and restoring

A method of testing a random access memory (RAM) for single V-coupling faults by establishing a first current value for each cell, for each cell and for each of m data backgrounds, generating a data bit corresponding to an element of an (n, V-1)-exhaustive matrix, and for each of m data backgrounds: (1) applying a read write sequence to each cell; and (2) for each background except the mth background, updating the current value of all cells according to the data bits corresponding to that cell; reading each cell of the RAM; and discarding or repairing the RAM if a cell coupling fault is apparent from the series of values read from the cells of the RAM. Data bits are generated by a matrix reconstruction method or a pseudo-random generator using a hashing of the address of the cell to which the data bit is to be applied. The logical function may be the element of the (n, V-1)-exhaustive matrix irrespective of the current of the cell or an exclusive-or of the complement of the background code logic bit and the first current value of the cell. Apparatus for testing a random access memory (RAM) has a PROM containing background code logic bits corresponding to an (n.sub.0, V-1)-exhaustive matrix where n.sub.0 .ltoreq.n, the matrix having n.sub.0 rows and m.sub.0 columns; and a data bit generator for generating data bits from the matrix stored in the PROM. A built in apparatus for testing a random access memory (RAM) having n cells includes a data bit generator that generates pseudo-random data bits from a hashing of the address of the RAM cell to which the data bit is to be applied.

Method and apparatus for testing electronic memories for the presence of

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Edmonton, Canada

Bruce F Cockburn