Motorola Corporation

Freescale Semiconductor,inc.

Bruce E White

Ramachandran Muralidhar

Michael Alan Sadd

Rajesh A Rao

Bo Jiang

Robert E Jones

Robert F Steimle

Craig T Swift

Bradley M Melnick

Robert Edwin Jones, Jr

Leo Mathew

Srikanth Balaji Samavedam

David L O'Meara

Erwin J Prinz

Sucharita Madhukar

Douglas R Roberts

Bich-Yen Nguyen

Sufi Zafar

Chitra K Subramanian

Olubunmi O Adetutu

Tab Allen Stephens

Peter Zurcher

Wayne M Paulson

Brian J Goolsby

Hideo Oi

Lakshmanna Vishnubholta

An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

Nanocluster charge storage device

A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.

Method of forming a finFET and structure

A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

Light erasable memory and method therefor

A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Nanocrystal non-volatile memory cell and method therefor

Method of forming a nanocluster charge storage device

A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer on the polysilicon gate and to re-expose the previously exposed portion of the metal layer. The re-exposed metal layer is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer. Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate but for the protection provided by the sidewall spacer. After the re-exposed metal has been removed, a transistor is formed in which the metal layer sets the work function of the gate of the transistor.

Method of making a metal gate semiconductor device

A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.

Non-volatile nanocrystal memory and method therefor

In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Method of discharging a semiconductor device

A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

Semiconductor device with nanoclusters

A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.

Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode

A multi-bit non-volatile memory device includes a charge storage layer () sandwiched between two insulating layers (and) formed on a semiconductor substrate (). A thick oxide layer () is formed over the charge storage layer () and a minimum feature sized hole is etched in the thick oxide layer (). An opening is formed in the thick oxide layer (). Side-wall spacers () formed on the inside wall of the hole over the charge storage layer have a void () between them that is less than the minimum feature size. The side-wall spacers () function to mask portions of the charge storage layer (), when the charge storage layer is etched away, to form the two separate charge storage regions (and) under the side-wall spacers (). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Multi-bit non-volatile memory device and method therefor

Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

Integration of two memory types on the same integrated circuit

A multi-bit non-volatile memory device includes a charge storage layer ( ) sandwiched between two insulating layers ( and ) formed on a semiconductor substrate ( ). A thick oxide layer ( ) is formed over the charge storage layer ( ) and a minimum feature sized hole is etched in the thick oxide layer ( ). An opening is formed in the thick oxide layer ( ). Side-wall spacers ( ) formed on the inside wall of the hole over the charge storage layer have a void ( ) between them that is less than the minimum feature size. The side-wall spacers ( ) function to mask portions of the charge storage layer ( ), when the charge storage layer is etched away, to form the two separate charge storage regions ( and ) under the side-wall spacers ( ). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

A heteroepitaxial structure is made using nanocrystals that are formed closer together than normal lithography patterning would allow. The nanocrystals are oxidized and thus selectively etchable with respect to the substrate and surrounding material. In one case the oxidized nanocrystals are removed to expose the substrate at those locations and selective epitaxial germanium is then grown at those exposed substrate locations. The inevitable formation of the misfit dislocations does minimal harm because they are terminated at the surrounding material. In another case the surrounding material is removed and the germanium is epitaxially grown at the exposed substrate where the surrounding material is removed. The resulting misfit dislocations in the germanium terminate at the oxidized nanocrystals. By using nanocrystals that are able to be formed much closer together than is available for other features through lithography, the misfits are prevented from extending so far as to create harmful threading dislocations.

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Round Rock, TX, United States of America

Bruce E White