Motorola Corporation

Bruce E Engles

Bruce L Morton

Daniel C Knightly

Perry H Pelley

Stephen T Flannagan

Scott G Nogle

Gianfranco Gerosa

Gary T Anderson

Michael H Chaddock

A multiplexed output circuit (200) for use in an integrated circuit (500) such as a static random access memory locates a plurality of amplifiers (206, 208), a plurality of output buffers (210, 212), and an output driver (201) on the integrated circuit (500), such that the routing parasitic delay between the plurality of output buffers and the output driver (218-224) is greater than the routing parasitic delay between any output buffer (e.g. 212) and its corresponding amplifier (e.g. 206).

Multiplexed output circuit and method of operation thereof

An integrated circuit memory (10) has a redundant column (20) located approximately in the middle a memory array (80, 81). Input/output (I/O) blocks (49, 70) are located on a periphery of the memory (10). A redundant multiplexer (24) is coupled to the redundant column (20) and to a top redundant global data line (36) and a bottom redundant global data line (34). Data is routed between the redundant columns (20) and the I/O blocks (49, 70) via the top and bottom redundant global data lines (36, 34) to effectively shorten the redundant global data line, thereby reducing the amount of redundant data line load capacitance. A fuse circuit (50) is used to program which of the top or bottom global data lines (36, 34) replaces a defective data path. This arrangement permits increased redundant array efficiency while achieving the required performance goals.

Integrated circuit memory with multiplexed redundant column data path

A non-volatile memory has memory cells which are programmable to a programmed state from an unprogrammed state. Programming changes the conductivity of the memory cell which is being programmed. The particular state of a selected memory cell is determined by comparing the conductivity of the selected memory cell to that of a normal reference. In order to assure that a memory cell has been programmed to a conductivity which is sufficient for reliable detection, a substitute reference with a different conductivity is used immediately after programming. If the selected cell is detected as being programmed when compared to the substitute reference, the selected cell is then determined to have been sufficiently programmed for reliable detection using the normal reference.

Program check for a non-volatile memory

A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.

Memory using distributed data line loading

A non-volatile memory has a sense amplifier having a select side and a reference side which compares the current drawn by a selected bit line to the current drawn by a reference bit line. There is a column decoder which selects the bit line and couples it to the select side of the sense amplifier. The column decoder adds capacitance so that the capacitance is greater on the select side of the sense amplifier than on the reference side. The natural result of the capacitance imbalance was slowing of the speed with which the sense amplifier could provide reliable sensing. There is provided circuitry for compensating for this capacitance imbalance.

Sense amplifier precharge control

An integrated circuit floating gate memory is formed using two layers of polysilicon. The first layer of polysilicon is patterned twice, once before the second polysilicon layer is deposited, and again as part of the etch of the second layer of polysilicon. Stringers of the second layer of polysilicon can form along the edge of the first etch of the first layer of polysilicon. The first etch of the first layer of polysilicon is patterned so that even if these stringers are subsequently formed, there is no harm.

Polysilicon pattern for a floating gate memory

A clock generator is used in a non-volatile memory to generate a timing signal for clocking a sense amplifier. The timing signal duration is timed using circuit features which also affect the rate with which data can be sensed by the sense amplifier. The clock generator includes a reference word line which is analogous to an accessed word line, a memory cell which establishes a reference current analogous to that provided by an accessed cell, and a current mirror which uses the reference current to charge a reference line analogous to a bit line. The duration of the timing signal is established by the reference line reaching a predetermined voltage.

Memory device including a clock generator with process tracking

A non-volatile memory has memory cells which have a first or a second conductivity. A reference current is established through an unprogrammed reference cell which has the first conductivity. A logic state current is established through a selected memory cell. The magnitude of the logic state current is related to the conductivity of the selected memory cell. A current comparator is used to compare the reference current to the logic state current. If the logic state current is related to the first conductivity state, an output signal is provided at a first logic state. If the logic state current is related to the second conductivity state, the output signal is provided at a second logic state.

Current mirror sense amplifier for a non-volatile memory

A multi-page ROM uses programmable pointers for selection of a page. The pointers each have a preliminary latch circuit, an output latch circuit, and a delay circuit. The preliminary latch circuit receives and stores program address signals when a first signal is present. The output latch receives the address stored in the preliminary latch when a second signal is present. The delay circuit removes the first signal before the second signal is present and delays the presence of the first signal for a delay period following the removal of the second signal.

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Austin, TX, United States of America

Bruce E Engles