Cypress Semiconductor Corporation

Bruce E Byrkett

Timothy John Williams

David Gordon Wright

Harold Kutz

Eashwar Thiagarajan

Mark E Hastings

Dennis Raymond Seguine

James H Shutt

Monte F Mar

Warren S Snyder

Bert Sullam

Gregory John Verge

Nathan Wayne Kohagen

Hans Klein

Jaskarn Singh Johal

Kendall V Castor-Perry

Erhan Hancioglu

Gajender Rohilla

Hans Van Antwerpen

Denis Ellis

Ata Khan

Daniel O'Keeffe

Carl Liepold

Jean-Paul Vanitegem

Amsby D Richardson, Jr

Onur Ozbek

Kevin J Gallagher

Anasuya Pai Maroor

Melany Ann Richmond

Kendall Castor-perry

Amsby Richardson

Jaskam Singh Johal

A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Combined analog architecture and functionality in a mixed-signal array

A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

Programmable input/output circuit

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Programmable switched capacitor block

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

A first portion of a programmable switched capacitor block includes a first plurality of switched capacitors and a second portion of the programmable switched capacitor block includes a second plurality of switched capacitors. A first switch associated with the first plurality of switched capacitors as well as a second switch associated with the second plurality of switched capacitors may be configured based on a type of analog function that is to be provided. The configuring of the first analog and the second analog block may include the configuring of the first switch associated with the first plurality of switched capacitors when the analog function operates on a first single ended signal and the configuring of both the first and second switches when the analog function operates on a differential signal.

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

Integrated circuit device with programmable analog subsystem

An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

Dynamically reconfigurable analog routing circuits and methods for system on a chip

A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.

A circuit for generating a voltage is disclosed. The voltage has an amplitude greater than an available power supply. The circuit includes a driver to supply the voltage on an output terminal to an electrode of a touch sense array. The circuit also includes a charge pump array coupled to the driver. The charge pump array includes an array of charge pumps to supply an input voltage to the driver. The circuit also includes a feedback circuit coupled to the charge pump array. The feedback circuit is configured to measure the input voltage and to select different combinations of the array of charge pumps to maintain the voltage on the output terminal.

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Preston, WA, United States of America

Bruce E Byrkett