Seagate Technology Incorporated

Maxtor Corporation

Quantum Corporation

Digital Equipment Corporation

Seagate Technologies, Inc.

Bruce Douglas Buch

Ara Patapoutian

Mark A Gaertner

Jon David Trantham

Bernardo Rub

Barmeshwar Vikramaditya

Ryan James Goss

Arvind Sridharan

Stefan Andrei Ionescu

Nick Horgan

Mehmet Fatih Erden

Belkacem Derras

Rose Shao

John VanLaanen

Michael John Link

Wenzhong Zhu

Michael L Mallary

Riyan Alex Mendonsa

Jianhua Xue

Jason Bryce Gadbois

Brian Thomas Edgar

Kevin Dean Fisher

Todd Michael Lammers

Kenneth A Haapala

William Michael Radich

Andrew Michael Kowles

Deepak Sridhara

Philip L Steiner

Bruce A Leshay

Javier Ignacio Guzman

Jon Karsten Klarqvist

Diana L Langer

Mathew Power Vea

Nicholas Paul Mati

Justin J Koller

Kyaw Sin Maung

Timothy Proch

Guy T Lawrence

Andrew Thomas Jaeb

Cecil D MacGregor

Devon Dallmann

Aaron P Weyer

Xiong Liu

Edward Charles Gage

James Fitzpatrick

Kim Yang Lee

James Gary Wessel

Tim Rausch

Kevin Arthur Gomez

Yan Wu

Lih-Jyh Weng

Thomas P Nolan

John B Shaw

Housan Dakroub

David Erich Tetzlaff

Timothy Francis Ellis

James Dillon Kiely

John West Dykes

Michael Anthony Moser

Michael D Leis

Raul Horacio Andruet

Pablo A Ziperovich

Jeffrey Vincent DeRosa

Russell W Brown

Peter A McEwen

Bengt Anders Ulriksson

Arun Balakrishnan

Charles M Riggle

Bin Liu

James David Sawin

Paul Michael Wiggins

John J McEwen, Legal Representative

Ravi Hebbar

Richard E Olsen

Eduardo Gentile Veiga

Julian I Gorfajn

Russel R Clemmons

Pei-hui Zheng

Matthew D Rench

Brian Nugent

Ning Li

Phillip L Steiner

Thomas Lau

Charles Paul Henry

John A Scaramuzzo

E William Bruce, Ii

Leo Lopez

Claud L Blevins

Geoffrey L Huebner

Festus Adelabu

An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.

Reduced latency I/O in multi-actuator device

A data storage device includes a first system-on-a-chip (SOC) associated with a first read transducer that accesses one or more magnetic disks of the data storage drive. The first SOC has a first read channel operable to receive data from the first read transducer. A second SOC is associated with a second read transducer that accesses the one or more magnetic disks of the data storage drive independently of the first read transducer. The second SOC has a second read channel operable to receive second data from the second read transducer. The first and second SOCs are coupled via a data bus that facilitates communicating the first and second data to a host via a first host interface.

Coupling multiple controller chips to a host via a single host interface

An apparatus includes a logical space and first and second physical spaces. The apparatus further includes a map in which first successive alternate logical elements of the logical space are mapped to successive adjacent physical elements of the first physical space, and second successive alternate logical elements of the logical space are mapped to successive adjacent physical elements of the second physical space. A control circuit employs the map to substantially concurrently manage storage of data extents into the first and second physical space by routing a first subset of the data extents into the first physical space, routing a second subset of the data extents into the second physical space, and splitting individual extents of a third subset of the data extents into sub-portions, with at least one of the sub-portions being routed to the first physical space and another sub-portion being routed to the second physical space.

Managing storage device media data rates

An apparatus comprises a plurality of servo controllers and a plurality of motor control circuits. Each of the plurality of motor control circuits has a primary serial interface (SIF) coupled to one of the plurality of servo controllers and at least one secondary SIF coupled to others of the plurality of servo controllers. Each of a plurality of independently controllable actuators is coupled to one of the motor control circuits. Each of the plurality of motor control circuits is configured to generate a compensated control signal using an actuator command received from the primary SIF and an actuator command received from the at least one secondary SIF. Each of the plurality of motor control circuits is configured to control movement of one of the plurality of actuators using the compensated control signal.

Motor control circuitry for multiple-actuator support

A computing system can be arranged to generate a range of different frequencies with at least one oscillator of a clock module prior to providing a first clock frequency to a controller with a channel selector of the clock module in response to a dither control circuit. A system operation may be executed with the controller before the first clock frequency is changed to a second clock frequency during the execution of the system operation as directed by the dither control circuit. The second clock frequency can be chosen from the range of different frequencies. The computing system may return to the first clock frequency at the conclusion of the execution of the system operation.

Computing system with power variation attack countermeasures

A chip configured with pin-strapping includes a configuration pin coupled to a resistor, the resistor coupled a configuration circuit configured to provide a threshold voltage at a sense time interval. A configuration vector may be determined by driving the configuration pin with high impedance, and sampling the configuration pin at sense time intervals such that the configuration vector corresponds to the time interval at which a threshold voltage is reached.

Configuration pin-strapping

One or more magnetic recording disks are coupled to a spindle motor, each of the disks having opposing recording surfaces. Two or more actuators are moveable independently over at least a first recording surface of the one or more disks. A first actuator of the two or more actuators comprises a first write head and a first read head. A second actuator of the two or more actuators comprises at least a second read head and may include a second write head. A controller is coupled to the two or more actuators and configured to write data to a track on the first recording surface using the first write head, and perform a read operation on the data written to the track using the second read head. The controller is also configured to verify that the data was successfully written to the track in response to the read operation. The read operation can be performed within less than one revolution of the first recording surface after the write operation.

Read-after-write methodology using multiple actuators moveable over the same magnetic recording disk surface

In certain embodiments, an apparatus may comprise a first output driver connected to a first output via a first trace and a second output driver connected to a second output via a second trace. The first output driver may be configured to output a first drive signal to the first output to drive the first output and the first drive signal may cause first induced noise in the second trace. Further, the second output driver may be configured to output a second drive signal based on the first drive signal where the second drive signal may reduce the magnitude of the first induced noise at the second output.

Noise cancellation in multitransducer recording

Apparatus and method for enacting data security in a data storage device, such as by protecting against a differential power analysis (DPA) attack. In some embodiments, a dithered clock signal is generated having a succession of clock pulse segments. Each of the clock pulse segments has a different respective frequency selected in response to a first random number and a different overall duration selected in response to a second random number. The different segment frequencies are selected by supplying the first random number to a lookup table, and the different segment durations are obtained by initializing a timer circuit using the second random number. The dithered clock signal is used to clock a programmable processor during execution of a cryptographic function.

Secure execution environment clock frequency hopping

One or more detectors detect data from respective one or more analog sources operable to read from a storage medium. A buffer pool is between the decoders and two or more detectors. The decoders are simultaneously operable, via the buffer pool, to independently decode the data from the one or more detectors.

Data storage device with one or more detectors utilizing multiple independent decoders

Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

Random number generation using switching regulators

In a device with first and second heads, the second head is held at a radial location over one or more disks via a second actuator that moves the second head. A position error of the second head is read while performing a seek with a first actuator, the first actuator moving the first head over the one or more disks. A mechanical transfer function is determined between the first actuator and the second actuator based on the position error of the second head. The mechanical transfer function is used to provide compensation for the second head via the second actuator in response to subsequent seek of the first actuator.

Method to re-characterize mechanical coupling used in multiple-actuator servo compensation

A data storage device includes first and second controllers that independently and simultaneously process data from a recording medium. The first and second controllers each have respective first and second buffer managers coupled to respective first and second buffer memories. The first and second buffer managers are coupled to each other via an inter-controller data bus. The first controller is configured to receive a contiguous memory request for a block data transfer client of the first controller. A first part of the request is fulfilled from the first buffer memory via the first buffer manager, and a second part of the request is fulfilled from the second buffer memory via the second buffer manager communicating with the first buffer manager via the inter-controller data bus.

Storage drive with multiple controllers having interconnected buffer managers

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Westborough, MA, United States of America

Bruce Douglas Buch