Sharp Laboratories of America, Inc

Sharp Kabushiki Kaisha Corporation

Sharp Microelectronics Technology, Inc.

Bruce Dale Ulrich

Sheng Teng Hsu

Tingkai Li

Yoshi Ono

David R Evans

Tue H Nguyen

Wei Gao

Fengyan Zhang

Lisa Stecker

Douglas James Tweet

Hong Ying

Yanjun Ma

Chien-Hsiung Peng

Masato Kobayashi

Jer-shen Maa

Wei Pan

Pooran Chandra Joshi

Lawrence J Charneski

Gerald W Maliszewski

Steven Roy Droes

Mark A Burgholzer

Ray A Hill

A grayscale mask made from semi-transparent film layers is provided, along with an associated fabrication method. The method provides a transparent substrate, such as quartz, with a surface. A first layer of a semi-transparent film having a surface with a first surface area, is formed overlying the substrate surface. At least a second layer of the semi-transparent film having a surface with a second surface area greater than the first surface area, is formed overlying the first layer. A first vertical region is formed having a light first attenuation parameter through the combination of substrate, first layer, and second layer. A second vertical region is formed having a light second attenuation parameter through the combination of the first layer and substrate, and a third vertical region is formed having a light third attenuation parameter through the substrate.

Semi-transparent film grayscale mask

An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO, ZnO, TiO, doped ITO, doped SnO, doped ZnO, doped TiO, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

Method for forming an iridium oxide (IrOx) nanowire neural sensor array

A method is provided for forming an error diffusion-derived sub-resolutional grayscale reticle. The method forms at least one partial-light transmissive layer overlying a transparent substrate. At least one unit cell in formed in the transmissive layer. The unit cell is formed by selecting the number of reduced-transmission pixels in the unit cell, and forming a sub-pattern of reduced-transmission pixels in the unit cell. The unit cell is sub-resolutional at a first wavelength.

Error diffusion-derived sub-resolutional grayscale reticle

A sub-resolutional grayscale reticle and associated fabrication method have been presented. The method provides a transparent substrate, and forms a plurality of coincident partial-light transmissive layers overlying the transparent substrate. A pattern is formed, sub-resolutional at a first wavelength, in at least one of the transmissive layers. If there are n transmissive layers, the reticle transmits at least (n+1) intensities of light. In one aspect, each of the plurality of transmissive layers has the same extinction coefficient and the same thickness. In other aspects, the transmissive layers may have different thickness. Then, even if the extinction coefficients are the same, the attenuation of light through each layer is different. The transmission characteristics of the reticle can be further varied if the transmissive layers have different extinction coefficients. Likewise, the transmission characteristics through the sub-resolutional patterns can be varied.

Sub-resolutional grayscale reticle

A method of fabricating a grayscale mask includes preparing a silicon wafer; depositing a layer of SiNdirectly on the silicon wafer; implanting Hions into the silicon wafer to form a defect layer; depositing a first layer of SiONdirectly on the SiNlayer; depositing a layer of SRO directly on the first layer of SiON; patterning and etching the SRO layer to form a microlens array in the SRO layer; depositing a second layer of SiONon the SRO microlens array; CMP to planarize the second layer of SiON; bonding and cleaving the planarized SiONto a quartz plate to form a graymask reticle; etching to remove silicon from the bonded structure; etching to remove SiONand SiNfrom the bonded structure; and cleaning and drying the graymask reticle.

Method of fabricating grayscale mask using smart cut&#xae; wafer bonding process

A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiOnanorods are formed over the substrate and intermediate electrode, and a TiOfilm may be formed overlying the TiOnanorods. The TiOnanorods and TiOfilm are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiOfilm is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiOfilm is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiOfilm from a top noble metal/Pt/Ti multilayered stack overlying the TiOfilm, which has been selectively etched to form separate top electrodes.

Nanorod sensor with single-plane electrodes

A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.

Method of etching a TE/PCMO stack using an etch stop layer

A method of fabricating a grayscale mask includes preparing a quartz wafer; depositing a layer of SiNon the quartz wafer; depositing a layer of titanium/TEOS directly on the SiNlayer on the backside of the quartz wafer; removing the layer of SiNfrom the front side of the quartz wafer; depositing a layer of SRO directly on the front side of the quartz wafer; patterning a microlens array on the SRO layer; etching the SRO layer to form a microlens array in the SRO layer; depositing a layer of titanium; patterning and etching the titanium layer; depositing a layer of SiONon the SRO microlens array; CMP to planarize the layer of SiONremoving the titanium/TEOS layer from the backside of the quartz wafer; bonding the planarized SiONto a quartz reticle plate; and etching to remove SiNfrom the bonded structure to form a grayscale mask reticle.

Method of fabricating a grayscale mask using a wafer bonding process

A method of fabricating a grayscale reticle includes preparing a quartz wafer substrate; depositing a layer of SRO on the top surface of the quartz substrate; patterning and etching the SRO to form an initial microlens pattern using step-over lithography; patterning and etching the SRO to form a recessed pattern in the SRO; depositing an opaque film on the SRO; patterning and etching the opaque film; depositing and planarizing a planarizing layer; cutting the quartz wafer into rectangular pieces sized to be smaller than a selected blank reticle; bonding the a piece a to selected reticle blank to form a grayscale reticle; and using the grayscale reticle to form a microlens array on a photoimager.

Method of making a grayscale reticle using step-over lithography for shaping microlenses

Methods of forming depositing a ferroelectric thin film, such as PGO, by preparing a substrate with an upper surface of silicon, silicon oxide, or a high-k material, such as hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide, depositing an indium oxide film over the substrate, and then depositing the ferroelectric film using MOCVD.

MOCVD PGO thin films deposited on indium oxide for feram applications

A method of fabricating a grayscale reticule includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticule; and using the reticule to pattern a microlens array.

Grayscale reticle for precise control of photoresist exposure

A method of selectively etching a three-layer structure consisting of SiO, InO, and titanium, includes etching the SiO, stopping at the titanium layer, using CFin a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the InOlayer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tin a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

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A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications

A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor

A method of forming a microlens array includes preparing a substrate; fabricating a photosensitive array on the substrate; depositing a layer of lens material on the photosensitive array; depositing and patterning photoresist on the lens material, wherein patterning includes forming a photoresist region having a solid curved upper surface and a substantially rectangular base on the lens material layer; developing the photoresist; reflowing the photoresist; and processing the lens material for form a microlens array.

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Beaverton, OR, United States of America

Bruce Dale Ulrich