Teledyne Industries, Inc.

Elantec, Inc.

Elantec Semiconductor, Inc.

Bruce D Rosenthal

Robert L Norris

Richard L Gray

A video sync slicing circuit is disclosed that employs an adjustable gain control (AGC) amplifier and circuitry that adjusts a gain of the AGC amplifier such that a blanking level of the video signal at an output of the AGC amplifier equals a blanking reference voltage. The slicing circuit includes a circuit that triggers a composite sync signal when a sync pulse of the video signal equals the fifty percent slicing level.

Video sync signal slicing using variable gain control

A differential analog memory cell provides output signals governed by precisely adjustable voltage levels having minimal drift. The memory cell comprises a pair of differentially connected floating gate MOSFETs, each MOSFET having its source connected to a common current source and its drain connected to one leg of a current mirror. The floating gate of each MOSFET is connected to one electrode of a tunneling capacitor and one electrode of a coupling capacitor. Voltages applied to the other electrode of the tunneling capacitor inject charges onto the corresponding floating gate, the voltage of which is determined by the size of the coupling capacitor. Output voltages taken from the drains of the floating gate MOSFETs can be precisely adjusted up or down by applying single polarity voltage pulses to one or the other injector nodes.

Differential analog memory cell and method for adjusting same

An improved voltage level shifting circuit is provided that employs a reference voltage translation circuit having its input at a fixed reference voltage, to bias the operating point of a substantially similar signal voltage circuit. The reference circuit generates a bias current in response to the reference voltage which is coupled back to buffers in the reference and signal translation circuits. The bias current maintains the operating point of the signal translation circuit close to the switching point determined by the reference voltage.

Level shifter circuit

A novel driver circuit and feedback loop is provided that improves the response time of the driver circuit and produces threshold voltages and hysteresis levels which are substantially independent of the supply voltage. The feedback circuit uses a pair of transistors connected in a cascode configuration to provide positive feedback from the output of the driver circuit and to control this feedback by means of the signal at the driver circuit input. By coupling the input voltages to the gate of a cascode transistor, the response time of the driver circuit is improved without disturbing its high input impedance. In addition, by replacing a transistor in the driver circuit input buffer with a current source, the threshold voltage of the driver circuit can be made substantially independent of the supply voltage.

Circuit for introducing hysterisis

A precision resistor comparator provides for the comparison and the resistive value of a first resistor with the predetermined resistive value of a second resistor. A differential comparator and level shifter provides a digital signal indicative of the relative magnitude of the first and second resistors. Another aspect of the present invention is the provision of the second resistor on a monolithic substrate with the resistor comparator circuit. The second resistor is provided with a temperature coefficient that is substantially independent of variances in its fabrication parameters and a resistance that can be trimmed, following fabrication, with substantially no effect on the temperature coefficient of the second resistor.

Monolithic resistor comparator circuit

A high-voltage MOS transistor structure and the manner of its fabrication are disclosed. The transistor structure is fabricated at the surface of a semiconductor layer or substrate where the structure includes first and second regions provided at the surface spaced apart from one another by an intervening portion of the semiconductor layer. The first and second regions are of a predetermined conductivity type. A third region is provided in the semiconductor layer adjacent the first region. The third region extends from the first region partially across the intervening portion of the semiconductor layer at the substrate surface toward to second region and then extends into the semiconductor layer under the first region. A channel is thus defined between the third region and the second region. The channel interface junction of third region defines an arc curving under the first region. The third region is also of the predetermined conductivity.

Drail-well/extension high voltage MOS transistor structure and method of

The reference circuit includes a current mirror for providing first and second current paths for the conduction of respective first and second currents. The current mirror imposes a current level relationship between the first and second currents. A load, preferably resistive, is provided in the first current path for predominantly establishing a predetermined level of the first current. A transistor having a temperature coefficient of a predetermined polarity and a resistor having a temperature coefficient of a complimentary polarity are provided in the second current path for providing temperature compensation. Finally, a load compensation stage is provided in the first and second current paths to provide a thermal compensation feedback path from the transistor and resistor compensation elements to permit stabilization of the first current level with respect to temperature.

Low-voltage, temperature compensated constant current and voltage

An adjustable current mirror, responsive to a single polarity balance control signal that may be derived using feedback, is described. The current mirror amplifier comprises first means for providing a first current path, the first means including reference transistor means for providing a current level control signal, issued relative to a reference potential, that corresponds to the current level of the first current path, second means for providing a second current path, the second means including current control transistor means for controlling the current level of the second current path, the current control transistor means being responsive to the current level control signal, and adjust transistor means, provided in series with the reference transistor means in the first current path, for adjusting the current level control signal by effectively modifying the reference potential, seen by the first means, in response to the balance control signal. The current balance between the first and second conduction paths may be directly modified by the resulting effective adjustment of the transconductance of the transistor means in the first conduction path with minimal addition of circuit components and a corresponding minimal impact on nominal current mirror amplifier circuit operation.

Growing community of inventors

Los Gatos, CA, United States of America

Bruce D Rosenthal