Honeywell Information Systems Inc.

Bruce C Keene

John M Woods

Two switching elements are cross-coupled in the standard bistable multivibrator arrangement. Two additional switching elements are added: one each in parallel with one of the switching elements forming the bistable multivibrator. The two wave forms under study are applied to the control gate of each of the additional switching elements. When both wave forms are in one state, the two additional switching elements are switched ON, effectively inhibiting bistable multivibrator action. The first wave form to change state results in its associated switching element switching OFF, which releases the bistable multivibrator circuit to assume the corresponding stable state, which observed differentially across the switching element forming the bistable multivibrator, is indicative of the wave form to first undergo transition. After the first wave form has undergone transition, the bistable multivibrator becomes insensitive to the subsequently occuring transition on the second wave form, and the circuit remains in the defined stable state until both wave forms again assume their previous state prior to transition, in which, once again, bistable multivibrator action is inhibited.

Wave form transition sequence detector

A data processing system includes as part of its power circuits, a number of converter circuits, each coupled to a different one of the power supply units which are to provide different voltages for distribution and use throughout the system. Each of the power supply circuits furnish a 24 volt dc power confidence signal to a central ac power input entry panel which applies the power confidence signals to the converter circuits. Each converter circuit includes an optically coupled isolator circuit which converts the 24 volt dc signal to a noise free low voltage logic level suitable for utilization by the low level high speed logic circuits included within the system. The output noise free low voltages provided by the converter circuits are in turn applied to a corresponding number of confidence input lines of a system interface unit which includes a plurality of ports, each port connected to a different module within the data processing system. The states of the low voltage logical level signals are stored in a status register. When the operating system determines that a unit is inoperative due to a power supply unit failure, it can logically disconnect the port having a module having the failure. Additionally, one of the converter circuits provides a second output signal which is used to enable the clock circuits during system power up only after the system has been placed in a known state.

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Phoenix, AZ, United States of America

Bruce C Keene