International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Renesas Electronics Corporation

Adeia Semiconductor Bonding Technologies Inc.

Advanced Micro Devices Corporation

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

International Business Corporation

Globalfoundries U.S. 2 LLC

Tessera LLC

Bruce Bennett Doris

Kangguo Cheng

Ali Khakifirooz

Alexander Reznicek

Pouya Hashemi

Ghavam G Shahidi

Hong He

Huilong Zhu

Ying Di Zhang

Oleg Gluschenkov

Kern Rim

Hariklia Deligianni

Eugene John O'Sullivan

Junli Wang

Steven J Holmes

Qing Liu

Nicolas J Loubet

Vijay Narayanan

Terence B Hook

Devendra K Sadana

Carl John Radens

Stephen W Bedell

Xin Miao

Dureseti Chidambarrao

Sivananda K Kanakasabapathy

Fee Li Lie

Shom Ponoth

Thomas N Adam

Jack Allan Mandelman

Rajiv V Joshi

Ajey Poovannummoottil Jacob

Michael A Guillorn

Isaac Lauer

Ruilong Xie

Tenko Yamashita

Veeraraghavan S Basker

Keith Kwong Hon Wong

Chih-Chao Yang

Brent A Anderson

Michael Patrick Chudzik

Qinghuang Lin

Roy Rongqing Yu

Juntao Li

Julien Frougier

Soon-Cheon Seo

Chandrasekharan Kothandaraman

Theodorus E Standaert

Chun-chen Yeh

Ramachandra Divakaruni

Josephine B Chang

Timothy Joseph Dalton

Christian Lavoie

Matthew Earl Colburn

Sanjay C Mehta

Edward J Nowak

Anthony K Stamper

David V Horak

Toshiharu Furukawa

Haining S Yang

Mark Charles Hakey

Hemanth Jagannathan

Charles W Koburger, Iii

Balasubramanian Pranatharthiharan

Heng Wu

Dominic Joseph Schepis

Arvind Kumar

Amlan Majumdar

Chen Zhang

Jeffrey W Sleight

Keith E Fogel

Kevin K Chan

Jack Oon Chu

Wilfried Haensch

Lawrence Alfred Clevenger

Takashi Ando

Daniel C Edelstein

Yun Yu Wang

Dechao Guo

Sampath Purushothaman

Cyril Cabral, Jr

Jingyun Zhang

Reinaldo Ariel Vega

Kenneth Parker Rodbell

Paul Michael Solomon

Supratik Guha

Herbert Lei Ho

Shreesh Narasimha

Elbert Emin Huang

John Edward Barth, Jr

Effendi Leobandung

Karthik Balakrishnan

Tak H Ning

Michael Rizzolo

Geng Wang

Xiuyu Cai

Katherine Lynn Saenger

Praneet Adusumilli

Oscar Van Der Straten

Chung-Hsun Lin

Richard Stephan Wise

A wearable monitoring system includes a first flexible substrate encapsulating a current ramping system to provide a current to an electrode in direct contact with a predetermined location of skin of a user to promote bodily fluid secretion, and a second flexible substrate placed over the predetermined location, the second flexible substrate having an integrated electrochemical sensor to determine bodily fluid concentration levels secreted through the skin.

Wearable device for monitoring bodily fluids

A deposition tool includes a vacuum chamber and a physical vapor deposition module including a target source in the vacuum chamber. The target source includes a target material for depositing on a workpiece. An evaporator module is independent of the physical vapor deposition module and is mounted within an enclosure in the vacuum chamber. A gate is configured to selectively open the enclosure to permit evaporation of a coating element to coat the target source in the physical vapor deposition module.

PVD tool to deposit highly reactive materials

A memory device that includes an magnetoresistive random-access memory (MRAM) stack positioned on an electrode, a metal line in contact with the electrode, and a sidewall spacer abutting the MRAM stack. The memory device also includes a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimensions than the first height portion abutting an outer sidewall of the sidewall spacer.

MRAM stack with reduced height

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Structure and process to tuck fin tips self-aligned to gates

A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.

Half buried nFET/pFET epitaxy source/drain strap

A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, forming a second magnetic tunnel junction stack on the spin conducting layer, and forming a dielectric spacer layer on surfaces of the spin conducting layer and the second magnetic tunnel junction stack. The second magnetic tunnel junction stack has a width that is less than a width of the first magnetic tunnel junction stack. Also, a width of the spin conducting layer increases in a thickness direction from a first side of the spin conducting layer adjacent to the second magnetic tunnel junction stack to a second side of the spin conducting layer adjacent to the first magnetic tunnel junction stack.

Double magnetic tunnel junction device

In an approach, a biomedical device comprises at least one electrode, wherein the at least one electrode is coupled with a computer chip; at least two chemical sensors, wherein the at least two chemical sensors are coupled with the computer chip; the computer chip, wherein the computer chip comprises: a semiconductor substrate, and a processor; a microfluidic structure, wherein the microfluidic structure is an inert elastomeric polymer; a power supply device coupled to the computer chip; and an antenna configured to send data collected onto the computer chip to a remote server. In an approach, a processor stimulating a cell sample. A processor senses the presence of at least two types of biomolecules released by the cell sample. A processor records data collected by the at least two chemical sensors. A processor sends the recorded data to a remote server.

Medical device for stimulating and sensing bioactivity

A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Dielectric isolated fin with improved fin profile

An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.

High retention eMRAM using VCMA-assisted writing

A method of forming a vertical transport fin field effect transistor device is provided. The method includes replacing a portion of a sacrificial exclusion layer between one or more vertical fins and a substrate with a temporary inner spacer. The method further includes removing a portion of a fin layer and the sacrificial exclusion layer between the one or more vertical fins and the substrate, and forming a bottom source/drain on the temporary inner spacer and between the one or more vertical fins and the substrate. The method further includes replacing a portion of the bottom source/drain with a temporary gap filler, and replacing the temporary gap filler and temporary inner spacer with a wrap-around source/drain contact having an L-shaped cross-section.

Wrap-around bottom contact for bottom source/drain

A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming an MTJ stack including a reference layer, a tunnel barrier layer formed on the reference layer, a free layer formed on the barrier layer, and a cap layer formed on the free layer. The method also includes performing ion beam etching (IBE) through each layer of the MTJ stack to form at least one MTJ pillar. The method also includes forming an isolation layer on sidewalls of at least the tunnel barrier layer, the isolation layer comprising a same material as that of the tunnel barrier layer. A combined width of the isolation layer and the tunnel barrier layer is equal to or greater than a width of at least one of the reference layer and the free layer.

Magnetoresistive random-access memory device

A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

MJT based anti-fuses with low programming voltage

An access system having a communication component that interfaces with a first device and a second device, where the first device is located inside or on an entity and coupled to a biological organism of the entity, and where the second device is located outside the entity and a controller component that controls a function of the first device, employing the communication component, to provide treatment to the biological organism of the entity coupled to the first device based on a request received from the second device.

Cranial access device

A magnetic tunnel junction (MTJ) containing device is provided that includes an undercut conductive pedestal structure having a concave sidewall positioned between a bottom electrode and a MTJ pillar. The geometric nature of such a conductive pedestal structure makes the pedestal structure unlikely to be resputtered and deposited on a sidewall of the MTJ pillar, especially the sidewall of the tunnel barrier of the MTJ pillar. Thus, electrical shorts caused by depositing resputtered conductive metal particles on the sidewall of the tunnel barrier of the MTJ pillar are substantially reduced.

Structured pedestal for MTJ containing devices

A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.

Integrating embedded memory on CMOS logic using thin film transistors

Growing community of inventors

Slingerlands, NY, United States of America

Bruce Bennett Doris