Altera Corporation

Other

Altera Corporaton

Alterm Corporation

Bruce B Pedersen

Andy Louie Lee

Richard G Cliff

Christopher F Lane

David Lewis

Srinivas T Reddy

James G Schleicher

Francis B Heile

David Wolk Mendel

Kerry S Veenstra

Sinan Kaptanoglu

Sergey Yuryevich Shumarayev

Joseph Huang

Wei-Jen Huang

Tony K Ngai

Cameron R McClintock

Henry Kim

Rakesh H Patel

David Edward Jefferson

Ketan H Zaveri

Victor Maruri

Chiakang Sung

Manuel M Mejia

Michael David Hutton

Craig S Lytle

Bonnie I Wang

Gregg William Baeckler

L Todd Cope

Richard Yuan

Rahul Saini

Vaughn Betz

Jim Park

Mike Hutton

Peter J Kazarian

Irfan Rahim

Rina Raman

Bahram Ahanin

Dirk Alan Reese

James Park

Paul Leventis

Ninh D Ngo

Andrew Leaver

Peter John McElheny

Vikram Santurkar

Fung Fung Lee

Chris Wysocki

Yow-Juang W Liu

Alexander Marquardt

David Chiang

James A Watson

John C Costello

Hock-Chuen So

Alok Shreekant Doshi

Jeffrey T Watt

Jinyong Yuan

Juju Joyce

Ting Lu

Wayne Yeung

Giles V Powell

Tim Michael Vanderhoek

Lu Zhou

Brian L Wong

Gary Lai

Robert R Bielby

Marwan A Khalaf

Robert Richard Noel Bielby

Sivaraman Chokkalingam

Yun Sum Wong

Tim Tri Hoang

Jon M Long

Stephen D Brown

Vinson Chan

Kumara Tharmalingam

Gabriel Quan

Michael Menghui Zheng

James G Schleicher, Ii

Andy Turudic

Chris Lane

David Samuel Goldman

Brent Alan Fairbanks

Allan Thomas Davidson

Neville Carvalho

Yean-Yow Hwang

Boris Ratchev

Kalyan Kankipati

Tarun Verma

Seungmyon Park

Peter Mcelheny

Mao Du

Greg William Baeckler

Larry Anderson

Yuen Ho Choi

Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

Systems and methods for detecting and mitigating programmable logic device tampering

An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.

Techniques for protecting security features of integrated circuits

Systems and methods for detecting and mitigating of programmable logic device tampering

Circuits, methods, and systems are provided for securing an integrated circuit device against Differential Power Analysis (DPA) attacks. Plaintext (e.g., configuration data for a programmable device) may be encrypted in an encryption system using a cryptographic algorithm. Ciphertext may be decrypted in a decryption system using the cryptographic algorithm. The encryption and/or decryption systems may obfuscate the plaintext, the ciphertext, and/or the substitution tables used by the cryptographic algorithm. The encryption and/or decryption systems may also generate cryptographic key schedules by using different keys for encrypting/decrypting different blocks and/or by expanding round keys between encryption/decryption blocks. These techniques may help mitigate or altogether eliminate the vulnerability of cryptographic elements revealing power consumption information to learn the value of secret information, e.g., through DPA.

Differential power analysis resistant encryption and decryption functions

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Omnibus logic element

An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may reside as part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may include erroneous bits that differ from the desired PUF response. The random number generator may generator a random number that masks the current PUF response, whereas the syndrome generator outputs a syndrome of the current PUF response. This information may then be passed to a separate error-correcting code (ECC) processor. The ECC processor may return information back to the secure subsystem, and the control circuitry may then obtain a corrected PUF response that matches the desired PUF response.

Secure physically unclonable function (PUF) error correction

The invention discloses a method of authenticating data stored in an integrated circuit. The method includes storing randomized data in the integrated circuit such that the randomized data occupies each address space of the memory circuit that is not occupied by the stored data. The method also includes generating a first digital signature using the integrated circuit in response to authenticating a concatenation of the stored data and the first copy of randomized data. The method further includes generating a second digital signature in response to authenticating concatenation of a manufacturer-provided copy of the stored data and the second copy of randomized data using a computer-implemented authentication application and authenticating the data stored in the integrated circuit according to whether the first signature matches the second signature.

Systems and methods for authenticating firmware stored on an integrated circuit

An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.

Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.

Systems and methods for preventing data remanence in memory systems

Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the programmable integrated circuit device with the configuration data or prevent such configuration. Control circuitry may also use the security requirement data to set security features within the device.

Setting security features of programmable logic devices

Circuitry and methods prevent unauthorized programming, or reprogramming, of a programmable device, by requiring a signature in the configuration data to match a signature previously stored in the programmable device. A programmable integrated circuit device includes an input for configuration data, and programming control circuitry operable to derive a current signature from the configuration data, examine a first bit stored in the programmable integrated circuit device, and when the first bit is in a first state, compare the current signature to a first predetermined signature stored in the programmable integrated circuit device and configure the programmable integrated circuit device according to the configuration data only when the current signature matches the first predetermined signature, and when the first bit is in a second state, configure the programmable integrated circuit device according to the configuration data without comparing the current signature to the first predetermined signature.

Method and apparatus for securing programming data of a programmable device

Systems and methods are disclosed for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks. In particular, one or more inputs are added to a block RAM such that when one or more of the inputs are asserted, the address input to the Block RAM may be incremented prior to being used to retrieve data contents of the block RAM. Thus, if address &#x3c;addr&#x3e; is provided to the block RAM and the address increment signal is asserted, data may be read from location &#x3c;addr+N&#x3e; instead of &#x3c;addr&#x3e;, where N may be an integer. Block RAMs with such address arithmetic may be used to implement wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.

Address arithmetic on block RAMs

Integrated circuits may be programmed using configuration data to implement desired custom logic functions. The configuration data may be generated using a logic design system in the form of a configuration bit stream. The logic design system may generate a hash value for the stream by performing multiple hashing operations on the stream in a direction from a trailing end to a leading end of the stream in a reverse direction with respect to the order of the stream. The system may append the generated hash value to the leading end of the stream, may encrypt the hash value, and may provide the stream to an integrated circuit. The integrated circuit may decrypt or otherwise authenticate the hash value, may generate multiple test hash values for the stream and may compare the test hash values to hash values in the stream to determine whether the stream is authentic.

Systems and methods for performing reverse order cryptographic operations on data streams

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San Jose, CA, United States of America

Bruce B Pedersen