Motorola Corporation

Bruce Allen Boeck

Stanley Michael Filipiak

Terry Grant Sparks

Rajan Nagabushnam

Jeff Thomas Wetzel

A tPEN layer (,) having a tensile stress is formed over a conductive gate stack (,) provided on a semiconductor substrate. Following the formation of the conductive gate stack (,), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (,) is formed and patterned to form a gate (,).

Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode

An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.

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Austin, TX, United States of America

Bruce Allen Boeck