International Business Machines Corporation

Bruce A Wagar

Erwin F Pfeffer

Lisa Cranton Heller

Ute Gaertner

Pak-kin Mak

Jane Helen Bartik

Patrick M West, Jr

Michael Billeci

Keith N Langston

Donald G O'Brien

Chung-Lung K Shum

David S Hutton

Norbert Hagspiel

Timothy J Siegel

Joerg Deutschle

Kathryn Marie Jackson

Richard Kirchhofer

Janice K Mead

Andrew Paul Gellai

Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.

Method and system for measuring the performance of a computer system on a per logical partition basis

The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.

Method for address translation in virtual machines

A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system cache. The building includes designating a number of sub-entries for each entry which is determined by a number of sub-entries operable for performing system cache coherency functions. The building also includes providing a sub-entry logic designator for each entry, and mapping one of the sub-entries for each entry to the system cache via the sub-entry logic designator.

Method and apparatus for implementing a combined data/coherency cache

A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.

Method, system, and computer program product for implementing a dual-addressable cache

A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache directories are substantially equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these separate cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors. The other cache directory retains only addresses, including addresses of lines LRUed out from the first cache directory and the identity of the processor using the data. Thus by this expedient, only the directory known to be backed by system cached data will be evaluated for system cache memory data.

Separate data and coherency cache directories in a shared cache in a multiprocessor system

Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set. Scrubbing can take place in the background, and can be suspended and resumed at any time so as to not impact request service times of the tables.

Buffered indexing to manage hierarchical tables

Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.

Blocking processing restrictions based on page indices

A method and system in accordance with the present invention overcomes the problem of program applications causing an overcommitment of a performance resource, while permitting full use of the performance resource by multiple concurrent applications. In such a method and system each program whose applications need access to a specific performance resource subscribe to a particular protocol to dynamically manage the available performance resource. This permits full use of the performance resource by all of the applications in the system without risk of overcommitting all the performance resource.

Method and system for dynamic performance resource management within a

An external data record sorting system that adaptively combines elements of both the distribution-based and the comparison-based sort procedures. The internal distribution-based sorting procedure generates sorted record strings that are twice as long on average as the available internal memory storage space. This MSB radix distribution procedure is adaptively optimized to data file characteristics by a predetermined threshold test that halts the distribution pass for a bin containing fewer records than a predetermined threshold number, which are then immediately sorted using a simpler comparison-based sorting procedure. This system also overlaps the input file reads and secondary storage writes between distribution sequences, thereby minimizing the non-overlapping portions of input/output operations and internal processing operations. As sorted records are written to secondary storage and new records are moved from the input file, the new records may be added to the current distributive sort tree, thereby minimizing the total number of strings created. Because new records are moved in from the input file concurrently with the removal of sorted records to the output area, the average output string can be twice the size of internal storage. By minimizing the number of strings that are later merged to complete the sort, overall external sorting procedure time is minimized.

Distribution-based replacement selection sorting system

A system and process for enhancing internal radix sorting bin storage efficiency by using linked blocks of contiguous storage space while controlling the number of partially-filled blocks required. The improved internal radix sorting procedure makes it possible to sort large computer files very efficiently without the risk of overflowing allocated storage space. A Most Significant Byte (MSD) radix sorting procedure avoids the collection step required in the LSD radix sorting procedure. The distribution pass is halted whenever a bin is found to contain less than a predetermined threshold number of records and the bin is then sorted immediately using a simple comparison-based sort. At each distribution rank, the system selects and sorts the smallest bins first, thereby quickly releasing storage blocks that may be required during the distribution sort passes for the larger bins. In this radix sorting procedure, the total number of linked storage blocks of size B can never exceed (R/B)+(1-1/B)A, where R is the total number of records to be sorted and A=(M-1) log.sub.M (R/T)+min (T,M)+1, where M=key field digit radix and T=bin size threshold for switching to comparison-based sort completion.

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Tempe, AZ, United States of America

Bruce A Wagar