Intel Corporation

Bruce A Tennant

Debendra Das Sharma

Michelle C Jen

Su Wei Lim

Mahesh U Wagh

Fulvio Spagna

Prahladachar Jayaprakash Bharadwaj

Quinn Devine

Minxi Gao

Noam Dolev Geldbard

Sin Sim Tan

Dan Froelich

Altug Koker

Srikanth T Srinivasan

Daniel S Froelich

Sivakumar Radhakrishnan

Ronald W Swartz

Poh Thiam Teoh

Hooi Kar Loo

Dmitry Petrov

Yick Yaw Ho

Yueming Jiang

Jennifer Chin

Hui Shi

Jasper Balraj

Athourina Gevergiz

Paulette Thurston

An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface

Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Flex bus protocol negotiation and enabling sequence

Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect

Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface

An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Reduced pin count interface

Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface

Systems, methods, and apparatuses are described for deskewing between multiple lane groups of deskewed data streams. Multiple distinct and deskewed lane groups can be aligned by utilizing an inter-group synchronized set of counters. The counters supply a way to measure the time delta (counter difference) in clocks between the multiple streams. Using this delta, one or more streams can be stalled to align the multiple streams. The counter values are communicated between the multiple groups in a way that they align to set data stream markers. These fixed markers and the breaking up of the counters in relation to the periodicity of the markers allows for a robust way to compare the multiple streams and calculate an accurate time delta.

Methods, apparatuses, and systems for deskewing link splits

Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Link equalization mechanism

A programmable link training and status state machine is disclosed. The programmable finite state machine includes extra states, or shadow states, which are strategically used to debug a system design or to accommodate unexpected behavior, such as when the specifications of the design change. The programmable finite state machine is thus a mechanism to design in correctable logic, enabling the logic to be corrected in silicon and used in succeeding iterations of a product line.

Method and apparatus to generate platform correctable TX-RX

Requests are identified for equalization coefficients and a plurality of coefficient selections are tracked relating to the requests. A matrix is maintained within a grid space that is to represent the coefficients, the matrix representing one or more of the coefficient selections. The matrix is adjusted within the grid space to obtain an adjusted matrix that is to accommodate selection of a particular coefficient outside the matrix. A final coefficient can be selected based on the adjusted matrix.

Method, apparatus, and system for sliding matrix scoreboard utilized in auto feedback closed loops

Growing community of inventors

Hillsboro, OR, United States of America

Bruce A Tennant