Motorola Corporation

Tanisys Technology, Inc.

Neosem Inc.

Bruce A Parker

Dong Hyun Yeom

Matthew L Carlson

Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test.

Memory device test apparatus and method having multiple memory devices connected to downstream ports of a PCI express switch at the same time

A trailer microprocessor in a debugging tool runs code a known number of cycles behind a master and shadow pair of processors. A pipeline queues up bus activity from the shadow processor a number of cycles, and then outputs those signals to the trailer microprocessor to execute the same code and signals as the master and shadow microprocessors a known number of cycles behind. The outputs of the master and shadow microprocessors are compared and the trailer microprocessor is halted, along with the master and shadow, when a 'mismatch' occurs between the outputs of the master and shadow processors. When the internal states of all three processors are scanned, the differences in the internal state of the shadow processor before and at a failure can be theoretically compared. The trailer microprocessor may be stepped cycle-by-cycle up to and past the point of failure of the shadow processor for further analysis.

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Austin, TX, United States of America

Bruce A Parker