International Business Machines Corporation

Bruce A Kauffmann

Chung H Lam

Jerome Brett Lasky

Roland A Bechade

Mark D Bolliger

An automated method for optimally ordering macros within a semiconductor chip data-path stack is disclosed. Each stack macro is assumed to have at least one predetermined bus connection with another macro in the stack. The ordering technique is based on minimizing for each macro in the stack the total number of stack macros passed by buses predeterminedly connected to that macro without making connection thereto. In addition, a macro group is formed of any subset of stack macros caught in a repeating loop. Each macro group contains at least two macros of the stack. Once defined, a macro group is treated as a single stack macro and optimization processing continues. Once the optimal location of all macros is identified, then any formed macro group is expanded and the optimal location of each macro within the group itself is identified. Specific details of the method are provided herein.

Stack macro order optimizing method

A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source defines a channel region in the substrate with an associated drain. An electrically isolated floating gate is disposed above the substrate so as to overlap at least a portion of the substrate channel region. Further, a program gate is disposed to overlap a portion of the floating gate and an access gate is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells can also be constructed.

Semiconductor memory cell and memory array with inversion layer

A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (T.sub.on) and low state (T.sub.off) intervals per cycle from a received clock signal having a substantially constant period but variable T.sub.on and T.sub.off intervals per cycle. The shaping network utilizes a set/reset latch to output the desired clock signal. The set input to the latch receives a set pulse generated at the beginning of each cycle of the received clock signal and the reset input to the latch receives a reset pulse generated by control logic circuitry. The logic circuitry uses the frequency of the received clock signal to generate a reset pulse at the appropriate time for gating of the latch to produce an output clock signal having the desired T.sub.on and T.sub.off intervals per cycle.

Process independent digital clock signal shaping network

A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode which has dual control gates disposed thereon. Each control gate includes a layer of dual electron injector structure (DEIS) and a polysilicon gate. When writing a '0' from the volatile storage capacitor to the floating gate, one of the control gates removes charge from the floating gate. To write a '1', the other control gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical. In order to minimize the adverse effects of process variations, the gate electrode of the word line device is electrically in common with one of the control gates.

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Jericho, VT, United States of America

Bruce A Kauffmann