Advanced Micro Devices Corporation

Hewlett-packard Development Company, L.p.

Bruce A Doyle

Emerson S Fang

Stephen F Greenwood

Shawn Searles

Alvin L Loke

Jingcheng Zhuang

Gregory L Ranson

Jayen J Desai

Michael Dreesen

Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.

Shared integrated sleep mode regulator for SRAM memory

A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Clock generator with integrated phase offset programmability

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

Oscillator with highly-adjustable bang-bang control

An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Passive filter and AC coupler receiver interface

Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output terminals and configured to detect a peak voltage level of the output signals and compare the peak voltage level with a reference voltage level; and an impedance element coupled to the comparator and the first and second output terminals, wherein the comparator is configured to provide a control signal to the impedance element to change the impedance of the impedance element to set a voltage variation of the output signals.

Interpolator systems with linearity adjustments and related methods

Systems, methodologies, media and other embodiments associated with peak detectors are described. One exemplary system embodiment includes a voltage peak detector comprising a first detector logic configured to detect a peak voltage of an input signal. The first detector logic has a circuit behavior that produces a leakage current that may alter the peak voltage. The system can also include a second detector logic configured to replicate the circuit behavior of the first detector logic including being configured to produce a replica leakage current that is equivalent to the leakage current. The second detector logic can be operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.

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Longmont, CA, United States of America

Bruce A Doyle