Sgs-thomson Microelectronics Limited

Cirrus Logic Inc.

Pixel Semiconductor, Inc.

Bruce A Doyle

Randy C Steele

William C Slemmer

Jyhfong Lin

John P Norsworthy

Jaideep Prakash

Safoin A Raad

A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion. Additionally, the biasing circuit minimizes noise coupling from ground potential to the D/A convertor output. A reset circuit is also included. This current cell, associated biasing stage, and reset circuit is suitable for applications requirement precise D/A conversions at high speeds.

Two cascoded transistor chains biasing DAC current cells

A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates a differential voltage, in response to feedback signals received from a first and second data outputs, dout1 and dour2, of the sense amplifier circuit, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a control signal .PHI..sub.2 ', complementary latched data outputs from the first and second data outputs, dout1 and dout2, generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a control signal .PHI..sub.0 ', voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. In addition, the voltage equalization stage is used to initiate the voltage developing stage. Timing of the control signals, .PHI..sub.0 ' and .PHI..sub.2 ', is such that the control signal .PHI..sub.2 ' is activated after a finite period following the deactivation of the second control signal .PHI..sub.0 '. To minimize power consumption of the sense amplifier circuit, the control signal .PHI..sub.0 ' is deactivated when either the voltage developing or full-swing locking stage is in operation and the voltage equalization stage is not needed.

Low-voltage high-performance dual-feedback dynamic sense amplifier

There is disclosed a circuit and method for providing a reference voltage to a matrix array of video DAC cells. The circuit is located substantially within a center of the matrix array in order to minimize any effects upon the delivered reference voltage that process variations within the integrated circuit supporting the video DAC may produce. The center location minimizes the average distance between the voltage reference circuit and each of the DAC cells within the matrix array. In a preferred embodiment, the circuit is divided so that a reference voltage supplied by one portion of the circuit is unaffected by inherent capacitances within the MOSFET devices utilized within the circuit coupling that voltage reference to the other reference voltages supplied by the second portion of the circuit. In another preferred embodiment, the circuit is supplied with a current from an external current source, the external current produced by an external voltage and an external precision resistor whereby the external current is regulated by comparing the external voltage to a second reference voltage produced by the external current, wherein the regulation of the external circuit is accomplished with a circuit utilizing an N-channel device in order to reference the external current to ground and not to a noisy voltage supply.

Voltage reference and current source for video DAC

A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator. The second charge-sharing capacitor, after sharing its charge with another capacitor inserted for purposes of circuit matching, is coupled to the other input of the differential amplifier, and the comparison is performed.

Temperature-compensated voltage level sense circuit

An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

Three transistor EEPROM cell

A shift register used to shift programming and test data into a programmable logic device is modified so that each bit thereof can be directly set or reset. Control signals can be used to directly place the required test patterns into the shift register. A memory connected to the shift register, and associated logic, provides a means for testing whether data was accurately written to the array without shifting any data off of the device.

High speed testing for programmable logic devices

A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.

Growing community of inventors

Richardson, TX, United States of America

Bruce A Doyle