Nvidia Corporation

Brijesh Tripathi

Duncan Andrew Riach

Michael A Ogrinc

Wayne Douglas Young

Wayne D Young

Adam E Levinthal

Stephen M Ryan

Patrick Rene Marchand

Robert Anthony Alfieri

One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Multiple simultaneous unique outputs from a single display pipeline

One embodiment of the invention sets forth a method for transmitting display data to a display device. The method includes the steps of receiving a contract for a frame of display data, preparing the frame of display data to ensure the timing requirements of the display device can be satisfied based on the contract, and transmitting the frame of display data to the display device while the contract is pending.

Isochronous hub contracts

A method of displaying an image includes generating a contract in the display engine, transferring the contract to the memory controller before the end of a sweep, generating a contract amendment in response to changes in the display engine, transferring the contract amendment to the memory controller, making a decision whether the contract amendment can be processed, fetching data from the memory controller according to the contract incorporating the contract amendment if the decision is that the contract amendment can be processed, sending the fetched data to the display engine in an isochronous stream; and processing the fetched data using the display engine.

Contract based memory management for isochronous streams

Apparatus, system, and method for detecting AC-coupled electrical loads of a set of digital-to-analog converters are described. In one embodiment, a processing apparatus includes a digital-to-analog converter. The processing apparatus also includes a pulse generation module connected to the digital-to-analog converter, and the pulse generation module is configured to direct the digital-to-analog converter to transmit a pulse of electrical energy. The processing apparatus further includes a load detection module connected to the digital-to-analog converter, and the load detection module is configured to determine a connection status of the digital-to-analog converter based on a degree to which the pulse of electrical energy is reflected during a transient response time period.

Apparatus, system, and method for detecting AC-coupled electrical loads

Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory request generator is configured to assign priorities to the memory requests based on a presentation order of the presentation elements. The processing apparatus also includes a memory request arbiter connected to the memory request generator. The memory request arbiter is configured to issue the memory requests based on the priorities assigned to the memory requests.

Apparatus, system, and method for arbitrating between memory requests

A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.

Apparatus, system, and method for delivering data to multiple memory clients via a unitary buffer

Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.

Growing community of inventors

Santa Clara, CA, United States of America

Brijesh Tripathi