Texas Instruments Corporation

Brijesh Rameshbhai Jadav

Mihir Narendra Mody

Niraj Nandan

Kedar Satish Chitnis

Shashank Dabral

Mayank Mangla

Vikram Vijayanbabu Appia

Anish Reghunath

Sujith Shivalingappa

Rajat Sagar

Jesse Gregory Villarreal, Jr

Hemant Hariyani

Lucas Carl Weaver

Ankur Ankur

Shiju Ozhuvinamolathu Sivasankaran

Rajasekhar Reddy Allu

Shyam Jagannathan

Anthony J Lell

Gang Hua

Prithvi Shankar Yeyyadi Anantha

Sivaraj Rajamonickam

Purushotam Kumar

Manjunath Rudranna Hadli

Vivek Vilas Dhande

Santhanakrishnan Narayanan Narayanan

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

Thread scheduling for multithreaded data processing environments

A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

Multi-channel system architecture for managing flow of data and associated trace information

A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

Dynamic configuration of perspective transformation engine

Systems and methods are provided for transmitting functional safety statistics within a system. A video source produces a video data stream. A functional safety system driver accumulates functional safety statistics from at least one system and writes the functional safety statistics onto an associated system memory. A display sub-system driver writes a frame of the video data stream to the system memory. The display sub-system driver formats the functional safety statistics as video data and appends the functional safety statistics to a portion of the frame of video that is reserved for the functional safety statistics. A display sub-system transmits the frame of the video data stream to a host processor, which extracts the functional safety statistics from the video frame.

Transmitting functional safety statistics via transmitted video

Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

Method and apparatus to facilitate low latency fault mitigation, QoS management and debug of a processing pipeline

A method for displaying a surround view on a single display screen is disclosed. A plurality of image frames for a particular time may be received from a corresponding plurality of cameras. A viewpoint warp map corresponding to a predetermined first virtual viewpoint may be selected, wherein the viewpoint warp map defines a source pixel location in the plurality of image frames for each output pixel location in the display screen. The warp map was predetermined offline and stored for later use. An output image is synthesized for the display screen by selecting pixel data for each pixel of the output image from the plurality of image frames in accordance with the viewpoint warp map. The synthesized image is then displayed on a display screen.

Three dimensional rendering for surround view using predetermined viewpoint lookup tables

A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

Reconfigurable image processing hardware pipeline

A video processor controlled by a set of non-shadow registers is provided. A list of updates for one or more of the non-shadow registers may be prepared in a memory module. A frame buffer is updated with video data for a display coupled to the video processor. A blanking interval is detected after updating the frame buffer. A direct memory access engine is triggered to transfer the list of updates from the memory module to the non-shadow registers during the blanking interval.

Updating non-shadow registers in video encoder

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Bengaluru, India

Brijesh Rameshbhai Jadav