International Business Machines Corporation

Briana E Foxworth

Kevin M Mcilvain

Lucas W Mulkey

Saravanan Sethuraman

Adam J McPadden

Edgar Rolando Cordero

Anuwat Saetow

Marc Avery Gollub

Irving G Baysah

Feihong Yan

Andre A Marin

In an approach to improve resolving defects within computer hardware, programs, software, or systems, embodiments pause mainline traffic and isolating interface or retention issues, and determine one or more types of errors in an event of a mainline traffic fail, wherein debug techniques are applied to fail information to resolve or further diagnose the one or more types of errors, and wherein the debug techniques are tracked and categorized. Additionally, embodiments apply corrective read actions to a detected error based on previously stored corrective actions associated with the detected error, and responsive to identifying no additional actions are required, restoring a collected system data. Further, embodiments, resume the paused mainline traffic.

Real-time error debugging

Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Thermal and power memory actions

An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

Memory security protocol

A method, system, and/or computer program product corrects a data error that has been caused by a break in a conductor link in a memory. A memory controller detects a line malfunction in a data bit transmission line between a first bit node and a second bit node in a memory, and then identifies a constant voltage state at the second bit node that is caused by the line malfunction. In response to determining that the constant voltage state is non-representative of the bit value intended to be transmitted from the first bit node to the second bit node, an inversion logic inverts bit values for all bits in an original bit array to create an inverted bit array, which is stored in the array of memory cells for future retrieval and re-inversion, in order to reconstruct the original bit array.

Correcting a data storage error caused by a broken conductor using bit inversion

An aspect includes viewing contents of a command queue that contains commands waiting to be sent in a specified order to a memory for execution at the memory. Command pattern data that includes patterns of commands and associated estimated power consumptions is accessed. The contents of the command queue are searched for the patterns of commands. One of the patterns of commands is located in the contents of the command queue. A suggested power management action is determined for the memory based on the located pattern of commands and its associated estimated power consumption. The suggested power management action is sent to a power control engine of the memory prior to a first command in the located pattern of commands being sent to the memory for execution.

Growing community of inventors

Round Rock, TX, United States of America

Briana E Foxworth