Altera Corporation

Brian Yung Fun Wong

Shankar Sinha

Shih-Lin S Lee

Abhishek B Sharma

Disclosed are apparatus and devices for programming and operating a programmable memory array portion coupled with a leakage reduction circuit. At the leakage reduction circuit, a frame bias signal that indicates a majority state of the memory array portion can be received. During idle states of the programmable memory array portion, at least one shared bit line of the memory array portion can be selectively biased based on the received frame bias signal. In one aspect, a first one of two bit lines is biased to a first state, while the second one of the two bits lines is biased to a second state that is opposite the first state. In a further aspect, the first state is a same state as the majority state of the memory array portion.

Systems and methods for reducing leakage current in memory arrays

Methods and apparatus are provided for conveying configuration data to a programmable logic device integrated circuit. When the configuration data is loaded into configuration memory on the programmable logic device integrated circuit, the programmable logic device integrated circuit performs custom logic functions. The programmable logic device integrated circuit or an associated configuration device integrated circuit may be provided with power conversion circuitry and transceiver circuitry. The power conversion circuitry converts received radio-frequency signals into power. The power from the power conversion circuitry is provided to the transceiver, loading, and configuration memory circuitry. The transceiver circuitry is connected to an antenna that receives wirelessly-transmitted configuration data and is used to transmit confirmation messages following successful loading of the configuration data into the configuration memory.

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San Jose, CA, United States of America

Brian Yung Fun Wong