International Business Machines Corporation

Globalfoundries Inc.

Brian William Thompto

Dung Q Nguyen

Hung Qui Le

Jose Eduardo Moreira

Jentje Leenstra

Sundeep Chadha

Albert James Van Norstrand, Jr

David Allen Hrusecky

Brian David Barrick

Richard James Eickemeyer

Robert Allen Cordes

Steven J Battle

Mohit Karve

Giles R Frazier

Salma Ayub

Michael K Gschwind

Lee Evan Eisen

Karl Michael Taylor

Younes Manton

Bruce Joseph Ronchetti

Andreas Wagner

Sheldon Bernard Levenstein

Michael Joseph Genden

Joshua W Bowman

John Barry Griswell, Jr

George W Rohrbaugh, Iii

Balaram Sinharoy

Phillip G Williams

Maarten Jakob Boersma

Christian Zoellin

Kurt Alan Feiste

Jose Angel Paredes

Jeffrey Carl Brownscheidle

Silvia Melitta Mueller

Susan Elizabeth Eisen

David R Terry

Dhivya Jeganathan

Tu-An T Nguyen

Benjamin W Stolt

Gregory William Alexander

James Wilson Bishop

Salim Ahmed Shah

Niels Fricke

Vivek Britto

Fadi Y Busaba

Bernard Charles Drerup

David S Levitan

Bryan J Lloyd

Markus Kaltenbach

Bradly George Frey

Kenneth Lundy Ward

Raymond Cheung Yeung

Nicholas R Orzol

Sam G Chu

Christian Jacobi

Brian Robert Prasky

Brett Olsson

Khary J Alexander

Brian William Curran

Elizabeth A McGlone

Jonathan T Hsieh

Maureen Anne Delaney

Debapriya Chatterjee

James R Mitchell

Mehul N Patel

Guy L Guthrie

Eric M Schwarz

Kirk David Peterson

Steven R Carlough

Karthick Rajamani

Michael Stephen Floyd

Charles Robert Lefurgy

Pratap Chandra Pattnaik

Malcolm Scott Allen-Ware

Mauricio J Serrano

Gregory Scott Still

Srinivasan Ramani

Todd Jon Rosedahl

Victor V Zyuban

Cliff Kucharski

Kimberly Marie Fernsler

Bodo Hoppe

Stefan Letz

Joerg Deutschle

Jafar Nahidi

Jessica Hui-Chun Tseng

Joshua D Friedrich

Ehsan Fatehi

Joel Abraham Silberman

Manoj N Kumar

Kattamuri Ekanadham

Scott Barnett Swaney

Sam Gat-Shang Chu

Deepak K Singh

David Andrew Schroter

John Andrew Schumann

Michael Klaus Kroener

John Wesley Ward, Iii

Christopher M Mueller

Edmund Joseph Gieske

A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Systems and methods for dynamic control of a secure mode of operation in a processor

A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.

Routing instructions in a microprocessor

A system, processor, programming product and/or method for assigning instructions to destination register file blocks, and/or routing instructions, includes: providing a processing pipeline having two or more execution units configured to process instructions; providing a register file having register file entries configured to hold data, where the register file is subdivided into a plurality of register blocks and each register block has two or more register file entries; calculating a utilization rate for one or more register blocks; and assigning and/or routing an instruction to write its results to a register block based upon the utilization rate for that register block. Preferably the execution unit is configured to write its results to a single specific destination (rename) register block.

Routing instruction results to a register block of a subdivided register file based on register block utilization rate

A processor unit for multiply and accumulate ('MAC') operations is provided. The present invention may include the processor unit having a plurality of MAC units for performing a set of MAC operations. The present invention may include each MAC unit having an execution unit and a one-write one-read (“1W/1R”) register file, where the 1W/1R register file may have at least one accumulator. The present invention may include the execution unit of each MAC unit being configured to perform a subset of MAC operations by computing a product of a set of values received from another register file of the processor unit and adding the computed product to the at least one accumulator. The present invention may include each MAC unit being configured to perform the respective subset of MAC operations in a single clock cycle.

Dispatching multiply and accumulate operations based on accumulator register index number

An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

A computer system, processor, computer program product, and method for executing instructions in a software application that includes a processor that can be dynamically controlled, in response to a value set in a control register, to operate in either a secure mode or a performance mode. In the secure mode, the processor: upon encountering a secure mode entry instruction, computes an entry hash value using a hash function and stores the entry hash value; and upon encountering a secure mode exit instruction, computes an exit hash value, loads the entry hash value, and determines whether the entry hash value is the same as the exit hash value, and depending upon verification of the hash values can execute the return function or transfer control to the operating system. In the performance mode, the processor: executes both the secure mode entry instruction and the secure mode exit instruction as no-operations.

Method and system for on demand control of hardware support for software pointer authentification in a computing system

Provided is a method for assigning register tags to instructions at issue time. The method comprises receiving an instruction for execution by a microprocessor. The method further comprises dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further comprises determining that the instruction is ready to issue. In response to determining that the instruction is ready to issue, the method comprises assigning an available register tag to the instruction. The method further comprises issuing the instruction.

Assignment of microprocessor register tags at issue time

An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.

Methods and systems for translating virtual addresses in a virtual memory based system

A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Loosely-coupled slice target file data

A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

Inferring future value for speculative branch resolution in a microprocessor

Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Compute array of a processor with mixed-precision numerical linear algebra support

A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Instruction handling for accumulation of register results in a microprocessor

Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

Microprocessor that fuses load and compare instructions

Growing community of inventors

Austin, TX, United States of America

Brian William Thompto