International Business Machines Corporation

Brian William Curran

Christian Jacobi

Fadi Y Busaba

Brian Robert Prasky

Khary J Alexander

Lee Evan Eisen

Edward Thomas Malley

Vijayalakshmi Srinivasan

Bruce C Giamei

David S Hutton

James R Mitchell

Brian William Thompto

Bruce Martin Fleischer

Gregory William Alexander

Jonathan T Hsieh

John G Rell, Jr

Sunil K Shukla

Avraham Ayzenfeld

Dung Q Nguyen

Alper Buyuktosunoglu

Anthony Saporito

James J Bonanno

Martin Recktenwald

Kailash Gopalakrishnan

Ruchir Puri

Chia-Yu Chen

John-David Wellman

Joseph L Temple, Iii

Jungwook Choi

Michael Thomas Vaden

Willm Hinrichs

David Allan Webber

Rafael Blanco

Jinwook Oh

Ashutosh Goyal

Eric M Schwarz

Hung Qui Le

David Arnold Luick

Brian David Barrick

James Douglas Warnock

Ching-Te Kent Chuang

Brian R Konigsburg

Tobias Webel

Prabhakar Nandavar Kudva

Swagath Venkataramani

Robert Dov Herzl

Tin-Chee Lo

David Andrew Schroter

Maureen Anne Delaney

Wen H Li

Preetham M Lobo

William Wu Shen

Gregory Allen Northrop

Richard Frank Rizzolo

Saiful Islam

George E Smith, Iii

Taqi Nasser Buti

Matthew A Krygowski

Sean Michael Carey

Jafar Nahidi

Leon Stok

Sanjay Bhikhubhai Patel

Mark D Mayo

Reinaldo A Bergamaschi

Frank P Cartman

Zakaria Mahmood Khwaja

Joseph M D'Onofrio

Richard N Fuqua

Louis J Milich

Paul M Moore

Sandy N Luu

Kailash Gopalakrishan

Matthew E Mariani

Lisa Bryant Lacey

Fadi Yusuf Busaba

Bruce Conrad Giamei

Khary Jason Alexander

An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

Microprocessor including an efficiency logic unit

Various embodiments are provided for implementing instruction initialization in a dataflow architecture in a computing environment. A data packet may be transmitted from a selected node to one or more of a plurality of nodes using one or more existing data paths in an initialization network. A determination operation is performed to determine whether one or more of a plurality of nodes is a target node intended for the data packet. Those of the plurality of nodes determined to be a target node initialize one or more components of the target node using the data packet. The data packet may be forwarded by each of the one or more of a plurality of nodes to a subsequent node in the initialization network.

Instruction initialization in a dataflow architecture

Embodiments of the present invention include a computer system that manages execution of one or more programs with one or more loops where each loop having a loop level. Embodiments that manage loops that can skip execution and the number of loops changing during execution are also disclosed. A loop level register (LLEV) stores the loop level for a currently executing loop. A Loop-Back Program Counter Register (LBPR) has a table of one or more Loop-Back Registers. Each Loop-Back Register stores the loop level for a LBPR respective loop and a loop back PC location for the LBPR respective loop. A Program Counter points back to the PC location for each iteration of the loop. A Loop Current Count Register table (LCCR) tracks a number of iterations remaining to executed for of the loop. A loop management process causes one of the CPUs to execute all the one or more instructions of an iteration of the currently executing program loop. When all iterations of the executing loop are complete, the LLEV is decremented to a next loop level that contained the executed loop.

Loop management in multi-processor dataflow architecture

Embodiments for implementing a communicating memory between a plurality of computing components are provided. In one embodiment, an apparatus comprises a plurality of memory components residing on a processing chip, the plurality of memory components interconnected between a plurality of processing elements of at least one processing core of the processing chip and at least one external memory component external to the processing chip. The apparatus further comprises a plurality of load agents and a plurality of store agents on the processing chip, each interfacing with the plurality of memory components. Each of the plurality of load agents and the plurality of store agents execute an independent program specifying a destination of data transacted between the plurality of memory components, the at least one external memory component, and the plurality of processing elements.

Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components

As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

Accelerated execution of execute instruction target

Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.

Structure for microprocessor including arithmetic logic units and an efficiency logic unit

A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.

Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit

Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.

Single-thread cache miss rate estimation

Single thread cache miss rate estimation

A processor is provided having a common supply rail, and one or more processor cores, where the one or more processor cores share the common supply rail. Each processor core(s) includes a core dIPC value output and a core throttling signal input, and a chip power management logic, which has at least one input for inputting the core dIPC value, a threshold register for a dIPC threshold value, a chip dIPC register for a current global dIPC value, at least one chip dIPC history register for a historic global dIPC value, a subtractor providing an absolute difference of an average historic global dIPC derived from the historic global dIPC value and the current global dIPC value, a magnitude comparator providing a throttling signal when the absolute difference is above the dIPC threshold value, and at least one output for outputting a core throttling signal to the processor core(s).

Voltage droop reduction in a processor

A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Accelerated execution of target of execute instruction

Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.

History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties

A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

Dual issuing of complex instruction set instructions

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Saugerties, NY, United States of America

Brian William Curran