Cortina Systems Corporation

Inphi Corporation

Nortel Networks Corporation

Brian Wall

Kenji Suzuki

Stephane Dallaire

Shawn Lawrence Scouten

Malcolm Stevens

Florin Pera

Colin Cramm

Lawrence Tse

Med Belhadj

Kevin Parker

Stephen Alie

Alex Nicolescu

Michael McDonnell

Split cascode circuits include multiple cascode paths coupled between voltage supply rails. Each cascode path includes a pair of controllable switches. A feedback path is provided for at least one of the cascode circuit paths. An active load circuit may also have a split cascode structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascode circuits.

Split cascode circuits and related communication receiver architectures

An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.

Apparatus and method for recovering data at an optical receiver with automatic tuning

Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.

A circuit having a component for signal recovery, such as an adaptive equalizer, may be tested in order to ensure that the component operates properly. Unfortunately, external test equipment may be expensive and prone to being damaged. According to an aspect of the disclosure, there is provided a circuit including BIST (Built-in Self-Test) circuitry for testing a component for signal recovery with a stress signal that simulates an imperfect signal received over a communication channel. The circuit also has a detector for determining whether the component is operating properly with the stress signal. Thus, no external test equipment is needed for testing the component. In some implementations, the BIST circuitry includes a low-pass filter for filtering a transmit signal into the stress signal. Thus, the amount of circuitry involved in generating the stress signal can be reduced.

Apparatus and method for self-testing a component for signal recovery

According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.

System and method for recovering data received over a communication channel

A novel method and apparatus is disclosed, that embeds with, or otherwise makes available to an adaptive equalizer, suitable for use in IEEE 1OG-LRM standard compliant receivers, digital logic that monitors some of the Layer 1 and preferably some of the Layer 2 processing that typically occurs after the equalization step during decoding and processing of the record data stream. From this additional logic information, the equalizer is able to make a much more accurate prediction of equalizer convergence by counting processing errors and prove convergence by calculation of BER. The novel method and apparatus are applicable to ASIC embodiments and the complexity of the logic information obtained can be programmably scaled back or enhanced as appropriate in light of the particular communication environment.

Method and apparatus for layer 1 / layer 2 convergence declaration for an adaptive equalizer

Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.

Signal timing phase selection and timing acquisition apparatus and techniques

The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.

Linear burst mode synchronizer for passive optical networks

An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.

Self correcting data re-timing circuit and method

A feed arrangement for a telephone subscriber loop. The feed arrangement includes an input for connection to a power supply and an output for connection to the TIP and RING conductors of the subscriber loop. A control element regulates the current in the subscriber loop to a target value selected in a set of possible target values. When the control element senses that an additional telephone instrument becomes active in the subscriber loop, a new target value is selected. The new target value is such that the current is sufficient to power all the telephone instruments that are currently active in the subscriber loop while low enough to avoid an excessive power dissipation at the feed arrangement and also to limit the power consumption.

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Stittsville, Canada

Brian Wall