Conexant Systems, Inc.

Synaptics Corporation

Brian W Friend

Lorenzo Crespi

Christian Larsen

Kyehyung Lee

Daniel L Essig

Chandrashekar Reddy Ayya

Stelian Mocanita

Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn.

Programmable gain amplifier systems and methods

Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to the PLL, a clock detect signal indicating whether the reference signal of the PLL is present or lost. The method further comprises continuously sampling and storing, by a loop sampler circuit connected to the PLL, a voltage from a loop filter of the PLL, when the reference signal is present. In addition, the method comprises configuring a charge pump of the PLL into a high impedance state, thereby disabling the charge pump, when the clock detect signal indicates that the reference signal is lost. Further, the method comprises supplying the voltage to the PLL to maintain a frequency of the output signal of the PLL, when the reference signal is lost.

Phase locked loop sampler and restorer

Systems and methods according to one or more embodiments are provided for a hum reduction circuit implemented to provide a ground path between an audio generating device and a powered headset. In one example, a system includes a jack configured to accept a plug comprising a first electrical ground connection. The system also includes a switch coupled to the jack at a first end and coupled to second electrical ground connection at a second end. The system also includes the switch is configured to couple to the first electrical ground at the first end. The system further includes a bias control signal coupled to the switch, configured to control a switch bias, where a first switch bias electrically couples the first electrical ground to the second electrical ground, and a second switch bias electrically decouples the first electrical ground from the second electrical ground.

Hum reduction circuit and method

A system for detecting a jack configuration comprising a first plurality of switches configured to couple a first headphone jack position to ground. A second plurality of switches configured to couple a second headphone jack position to ground. A microphone bias circuit for applying a microphone bias signal to the second headphone jack position when the first headphone jack position is coupled to ground, and for applying the microphone bias signal to the first headphone jack position when the second headphone jack position is coupled to ground.

Multi-standard headset support with integrated ground switching

A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.

Adaptive biasing technique for audio circuitry

A current comparator comprising a first NMOS transistor having a drain coupled to V, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to Vand a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to V, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

Low power current comparator for switched mode regulator

A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.

Audio programmable gain amplifier with automatic reconfiguration

A circuit for implementing a first order noise shaping apparatus for use in data converters employing thermometer-code based elements is disclosed. Raw thermometer code is rotated by up to four columns of shifters such that the code is rotated up to 15 positions. In this manner, the elements of the data converter may equally participate in the conversion process, thereby minimizing the effects of mismatched elements in a data converter by distributing errors due to mismatched elements. Such a process may be used in digital to analog converters and analog to digital converters such that a suitable data weighted algorithm can be used.

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Carlsbad, CA, United States of America

Brian W Friend