Xilinx, Inc.

Interval Research Corporation

Tyzx, Inc.

Intel Corporation

Microsoft Technology Licensing, LLC

Borealis Technical Limited

Vulcan Patents LLC

Environmental Security Corporation

Brian Von Herzen

Henry Harlyn Baker

John Iselin Woodfill

Robert Dale Alkire

Jonathan Sidney Edelson

David P Schultz

Navin Chaddha

Richard A Wotiz

Jon A Brunetti

Richard G Shoup

Glenn R Rink

A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data.

Generation of a disparity result with low latency

A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) andstatic random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations are disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region has one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern offset from one another responsive to the offset region.

Interconnect array formed at least in part with repeated application of an interconnect pattern

Data processing system and method

An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region having the one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern off-set from one another responsive to the offset region.

A disclosed fluid purity monitoring system employs a network of preferably information-transmissive cables fixed in place within a body of fluid. Sensors sensitive to fluid impurities are supported at various places on the network. Data representative of impurity levels transmits to a collection point via the same cables at which the sensors are supported. One system employs at least two pluralities of sensors sensitive to different fluid impurities. Another system employs electrically conductive cables fixed in place substantially in a common plane, with some cables oriented substantially parallel to each other and intersecting other cables. In that system, the data transmits to the collection point via a separate electrical circuit for each one of the sensors. Each circuit includes a series connection of the pair of cables that intersect proximate to the sensor's support point on the network. Advantageous variations and methods are also disclosed.

Distributed sensor array for fluid contaminant monitoring

Described are a system and method for converting a typical two-level logic signal to a pair of differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output terminals. A resistor network connected to these output terminals converts the complementary signals to a pair of differential signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.

Circuit for converting a logic signal on an output node to a pair of low-voltage differential signals

A polyphase induction motor is operated by an inverter drive system comprising a logic level controller. A number, preferably twelve or more, of independently driven phases causes harmonic fields, up to a number equal to the number of phases, to oscillate in synchrony with the fundamental oscillating field. A pulse-width modulation (&ldquo;PWM&rdquo;) carrier is used by the logic level controller to synthesize a desired drive alternating current, in which the pulsing distortion produced by the pulse width modulation produces a synchronous oscillating field in the driven polyphase induction motor.

Drive wave form synchronization for induction motors

A semiconductor chip integrating various functional blocks of a video codec for use in a system for real time record and playback of motion video through a computer interface such as a PC-compatible parallel port is disclosed. An innovative combination of the hardware implementing data compression and decompression based on a vector quantization algorithm with video input/output port and computer interface integrated on a single semiconductor chip provides for a cost-effective solution to processing of continuous-steam video and audio data in real time.

Video codec semiconductor chip

A hierarchical memory for use in a programmable gate array integrated circuit comprises an interconnect structure having a plurality of interconnect nodes electrically connected in a tree configuration. The interconnect nodes include a root node which receives a multi-bit address word indicative of a selected memory location. The hierarchical memory further includes a plurality of memory cells electrically connected to the interconnect structure to form leaf nodes of the tree. Each of the memory cells contains at least one memory location for storing binary data. The interconnect structure is traversed from the root node to a memory cell containing the selected memory location based upon the multi-bit address word, wherein the interconnect structure provides a communication path for accessing the selected memory location from the root node.

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Carson City, NV, United States of America

Brian Von Herzen