Arm Limited

University of Michigan

Brian Tracy Cline

Saurabh Pijuskumar Sinha

Mudit Bhargava

Vikas Chandra

Xiaoqing Xu

Stephen Lewis Moore

George McNeil Lattimore

Gregory Munson Yeric

Shidhartha Das

Gary Dale Carpenter

Andy Wangkun Chen

Azeez Jennudin Bhavnagarwala

Renee Marie St Amant

Peter James Samuel Ferguson

Kyungwook Chang

Lucian Shifren

Yew Keong Chong

Gus Wai-Yan Yeung

Marlin Wayne Frederick, Jr

Sriram Thyagarajan

Betina Hold

Paul Christopher De Dood

Greg Yeric

Daniel J Albers

Tom Shore

Divya Madapusi Srinivas Prasad

Ebbin Raney Southerland, Jr

Vinay Vashishtha

Jerry Chaoyuan Wang

David William Granda

David Theodore Blaauw

Bal S Sandhu

Robert Campbell Aitken

Dennis Sylvester

Rahul Mathur

Amit Chhabra

Thanusree Achuthan

Yejoong Kim

Naveen Suda

Yanbin Jiang

Brian Douglas Ngai Lee

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

Sylvia Xiuhui Li

Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

Optical waveguide connecting device

Subject matter disclosed herein may relate a communication interface to read from and/or to write to one or more entries of a bio-ledger and/or a biosphere ledger of a particular individual stored at a secure storage device and at least one processor to generate signals and/or states representative of behavioral profile content for a particular user based, at least in part, on signals and/or states obtained from one or more sensors, wherein the at least one processor to identify or predict, or a combination thereof, a change in omic state for the particular individual based at least in part on the one or more bio-ledger entries, the behavioral profile content, or the one or more biosphere ledger entries, or a combination thereof.

Systems, devices, and/or processes for OMIC and/or behavioral content processing

Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

Bitcell architecture

A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

Method and apparatus for generating three-dimensional integrated circuit design

According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

TSV coupled integrated circuits and methods

Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

Dielet design techniques

Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

Wirelength distribution schemes and techniques

Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized locations or legal locations.

Multi-tier co-placement for integrated circuitry

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array

Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.

Spiking neural network

Subject matter disclosed herein may relate to at least one processor to establish a communication connection between a portable computing device and a particular external device, the at least one processor to initiate transmission of one or more signal packets representative of one or more communication, security, and/or cryptographic parameters to the particular external device responsive at least in part to the establishing the communication connection.

Systems, devices, and/or processes for OMIC content processing and/or communication

Subject matter disclosed herein may relate to at least one processor to selectively authorize requests from one or more external devices to read from and/or write to particular bio-ledger entries and/or particular biosphere ledger entries based, at least in part, on security tokens provided by the one or more external devices and based, at least in part, on first and/or second sets of particular authorizations.

Systems, devices, and/or processes for omic content processing and/or partitioning

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

Computer implemented system and method for generating a layout of a cell defining a circuit component

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Method, system and device for integration of volatile and non-volatile memory bitcells

A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

Method for generating three-dimensional integrated circuit design

Growing community of inventors

Austin, TX, United States of America

Brian Tracy Cline