Xilinx, Inc.

Marvellworld Trade Ltd.

Marvell International Limited

Silicon Laboratories Inc.

Itron Gmbh

Alert Core, Inc.

Brian Taylor Brunn

Gregory Takeo Uehara

Sehat Sutardja

Alexander Zaslavsky

Ahmed Younis

Marc Leroux

Michael A Nix

Xiaohua Fan

Alessandro Venca

Firas Najeh Abughazaleh

Shahriar Rokhsaz

Brian Karl Seemann

Moises Emanuel Robinson

Jinghui Lu

Stephen D Anderson

Qiang Li

Charles Walter Boecker

Rinaldo Castello

Fernando De Bernardinis

Rony Ashkenazi

Paul Zavalney

Chao Yang

Ruoxin Jiang

Normand T Lemay, Jr

John W MacConnell

Luca Romano

Eric W Lofstad

Stefano Dal Toso

Antonio Milani

James M Simkins

David Erich Tetzlaff

Michael J Gaboury

Ramesh Harjani

Rangakrishnan Srinivasan

David B Squires

Chester Yu

Thomas Anthony Lee

Jari Juhani Vahe

Daniel J Ferris, Iii

Adrianus Josephus Bink

Michael Ren Kent

Yvette P Lee

Hegong Wei

Eric Sadowski

Rui Deng

Kazi S Hossain

Zhiguo Wang

Rohit Mainkar

Laurent Maleysson

Marck Leroux

In one embodiment, an apparatus includes: a clock generator to receive a reference clock signal and generate a first clock signal using the reference clock signal; a counter coupled to the clock generator to maintain a first count regarding a number of cycles of the first clock signal; and a controller coupled to the counter. The controller may be configured to detect a potential security violation when the first count varies from a predetermined value.

Detecting possible security violations in an integrated circuit

A circuit for compensating for data delay is disclosed. The circuit utilizes an internal clock signal. This internal clock signal passes through an I/O buffer to become an external clock. This external clock is then passed through the I/O buffer to create the return clock signal. This difference between the internal clock signal and the return clock signal is defined as I/O delay. In certain embodiments, this I/O delay may be more than one clock period, which typically causes incorrect operation of synchronous logic. The present circuit allows for a I/O delay of N clock periods, wherein N is greater than one, through a novel approach to capturing and synchronizing the return data. This allows high speed microcontrollers to utilize lower speed I/O buffers to reduce interference, or allows these microcontrollers to interface with slower external devices.

Data delay compensator circuit

An integrated circuit includes a digital circuit and an energy management circuit. The digital circuit operates with an internal power supply voltage in synchronism with a clock signal and comprises complementary metal-oxide-semiconductor (CMOS) transistors. The energy management circuit has an input for receiving an external power supply voltage and an output for providing the internal power supply voltage. The energy management circuit is thermally coupled to the digital circuit and sets the internal power supply voltage to a nominal voltage when a temperature of the digital circuit is greater than a boost temperature. The energy management circuit boosts the internal power supply voltage to a boosted voltage greater than the nominal voltage when the temperature of the digital circuit is less than the boost temperature.

Integrated circuit with enhanced operation over operating ranges utilizing a process signal to fine tune a voltage boosting operation

An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

Integrated circuit clock management during low power operations

Embodiments disclosed include a system and method for development of core muscles' support, comprising a means for identifying a user qualifying movement, a means for detecting a core muscle contraction in the identified qualifying movement, a means for discriminating between a core muscle contraction and no core muscle contraction in the identified qualifying movement; and a means to provide feedback to the user.

System, apparatus, and method for promoting usage of core muscles and other applications

Aspects of the disclosure provide a circuit that includes an envelope processing circuitry and a voltage modulator. The envelope processing circuitry is configured to receive a stream of envelope values of a signal for transmission and output a supply modulation signal in response to the stream of envelope values based on an average-power-tracking (APT) calibration. The voltage modulator is configured to modulate a supply voltage to an amplifier according to the supply modulation signal. The amplifier operates under the supply voltage to amplify the signal for transmission.

Method and apparatus for envelope tracking calibration

A circuit comprises a vector separator circuit to generate a first extracted signal according to (i) a first correlation signal, (ii) a second correlation signal, and (iii) a relative response signal. The first correlation signal corresponds to a first correlation between an input signal and a first test signal. The first test signal has a first frequency, and the input signal includes a first spur having the first frequency. The second correlation signal corresponds to a second correlation between the input signal and a second test signal. The second test signal has a second frequency. The relative response signal corresponds to a relative response of the second frequency in the first correlation signal.

Interference cancellation

A method includes setting a circuit to a mode. A test tone having a first frequency is provided to the circuit for use in calibrating the circuit. A received signal is generated based on an output signal of the circuit, the received signal including a component having a second frequency that is a harmonic of the first frequency. A magnitude of the component having the second frequency in the received signal is measured. A delay of the circuit corresponding to the mode is adjusted according to the magnitude of the component.

Method and apparatus for calibrating time alignment

In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Transmit architecture for wireless multi-mode applications

A wireless communications system includes a clock module, a global positioning system (GPS) module, an integrated circuit for a cellular transceiver, and a baseband module. The clock module is configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). The GPS module is configured to operate in response to the first clock reference. The integrated circuit includes a system phase lock loop (PLL) configured to (i) operate in response to the first clock reference, and (ii) generate a corrected clock reference by performing AFC on the first clock reference in response to an AFC signal. The baseband module is configured to (i) operate in response to the first clock reference from the clock module, and (ii) generate the AFC signal.

Wireless communications system including dual-purpose clock reference for global positioning system and baseband

A receiver including a mixer, a clock generator, a plurality of capacitances, a plurality of resistances, and a controller. The mixer includes a plurality of switches. The clock generator is configured to generate clock signals to drive the plurality of switches of the mixer. The plurality of capacitances couples the clock signals to respective inputs of the plurality of switches. The plurality of resistances couples to the respective inputs of the plurality of switches. The controller is configured to output a first signal to the plurality of resistances. The first signal determines one or more attributes of the clock signals. One or more switching characteristics of the plurality of switches of the mixer are based on the one or more attributes of the clock signals.

Mixer circuits with programmable characteristics

A wireless communications system includes a clock module, a communications module, a receiver module, and a baseband module. The clock module is configured to generate a first clock reference. The communications module is configured to operate in response to the first clock reference and independent of a corrected clock reference. The corrected clock reference is generated by performing automatic frequency correction on the first clock reference according to an automatic frequency correction signal. The receiver module is configured to (i) receive radio frequency signals from a wireless medium, and (ii) in response to the corrected clock reference, generate baseband signals based on the received radio frequency signals. The baseband module is configured to (i) receive the baseband signals, and (ii) in response to a selected one of the first clock reference and the corrected clock reference, generate the automatic frequency correction signal based on the baseband signals.

Clock multiplexing for baseband automatic frequency correction

Aspects of the disclosure provide a circuit that includes a first circuit, a second circuit, and an adder. The first circuit is configured to generate a first signal by outputting and holding, at a first timing, a first stream in response to an input stream of data. The second circuit is configured to generate a second signal by outputting and holding, at a second timing, a second stream in response to the input stream of data. The adder is configured to add the first signal with the second signal to generate an up-sampled stream for the input stream of data and reduce a frequency component in the up-sampled stream generated by the up-sampling.

Method and apparatus for envelope tracking

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Bee Cave, TX, United States of America

Brian Taylor Brunn