Xerox Corporation

Brian T Ormond

Josef E Jedlicka

Kraig A Quinn

Paul Allen Hosier

Thomas Grimsley

Gary Alan Kneezel

Jagdish C Tandon

Almon P Fisher

Daniel E Kuhman

Lawrence H Herko

Debra S Vent

Allan F Camp

Josef E Jedicka

Ackerman C John

A method of forming a semiconductor structure from a first wafer and a second wafer. A pit or groove is formed in a lower surface of the first wafer. The lower surface of the first wafer is bonded to an upper surface of the second wafer. A groove is then formed on an upper surface of the first wafer, such that an opening is formed in the first wafer that exposes at least one alignment reference target on the upper surface of the second wafer. The bonded first wafer and second wafer is then diced using the exposed at least one alignment reference target to form a semiconductor structure.

Methods of forming semiconductor structure

The present invention relates to electro optical devices with a reduced filter thinning on the edge pixels and a method for reducing the thinning of filter layers on the pixels closest to the edge of an electro optical device such as a photosensitive chip, as would be used, for example, in a full-color digital copier or scanner. A semiconductor wafer includes a main surface defining a plurality of chip areas and tab regions separated by grooves, wherein the chip areas include inner photosites, outer photosites and bonding pads. A plurality of dams are deposited over the main surface in the tab regions, and a clear layer is deposited over the main surface exclusive of the bonding pads. Alternatively, a clear layer is deposited over the main surface exclusive of the bonding pads, and a plurality of tabs is then deposited in the tab regions on the main surface. A first primary color filter layer is deposited over at least first inner photosite and first outer photosite, and the first primary color filter layer transmits a primary color.

Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same

The present invention relates to semiconductor devices with a reduced filter thinning of outer photosites and a method for reducing the thinning of filter layers of the outer photosites. A semiconductor device includes a main surface including a plurality of photosites and bonding pads defined in the main surface, wherein the photosites include inner photosites and outer photosites. The semiconductor device further includes a clear layer deposited over the main surface exclusive of the bonding pads and outer photosites, and a first primary color filter layer deposited over at least first inner photosite and first outer photosite, the first primary color filter transmitting a primary color.

Semiconductor chips, such as photosensor arrays for a full-page-width scanner or printhead chips for a full-page-width ink-jet printer, are mounted on a substrate to maintain reasonably consistent spacing among adjacent chips. To remove a defective chip from the array, the substrate is urged evenly against a work surface defining a convex bow. Alternately, back-cuts are provided along abutting edges of the chips, and the silicon around these back-cuts can be sawed away to space defective chips from neighboring good chips.

Replacing semiconductor chips in a full-width chip array

Semiconductor chips for use in a chip array assembly for scanning of hard-copy images include rows of photosensors, each row of photosensors having a polyimide filter layer for passing one primary color. In addition to the photosensors, a reflective area is provided on the chip, with filter portions provided on the reflective area. The filter portions are created at the same time as the filter layers placed on the photosensors. The filter layers disposed on the reflective area can be used as test sites for determining the light transmissivity of the filter layers on the photosensors.

Reflective test patches for translucent color filters in photosensitive

Semiconductor chips, such as photosensor arrays for a full-page-width scanner or printhead chips for a full-page-width ink-jet printer, are mounted on a substrate to maintain reasonably consistent spacing among adjacent chips. To remove a defective chip from the array, the substrate is urged evenly against a work surface defining a convex bow. Alternately, back-cuts are provided along abutting edges of the chips, and the silicon around these back-cuts can be sawed away to space defective chips from neighboring good chips. By increasing the spacing of a defective chip from neighboring chips, the defective chip can be removed while minimizing the risk of damage to neighboring chips. Also, batches of chips can be originally manfactured on a single wafer as either 'regular' chips or 'replacement' chips, with the replacement chips being slightly shorter in a critical dimension.

In an array of butted silicon chips, as would be found in a full-page photosensitive scanner, ink-jet printhead, or LED exposure bar, individual silicon chips forming the array each define a planar bevel near the border of a neighboring chip. The planarity of the bevel avoids damage to the chips when the chips are placed in the chip array assembly.

Butted chip array with beveled chips

A photosensitive chip, such as used in a scanner or facsimile, defines a linear array of photosites, each photosite being covered with a filter formed from a cured translucent liquid. At the critical ends of the chip, between the end photosite in the array and the edge of the chip, there is provided a ridge which protrudes over the thickness of the filter. This ridge maintains the physical integrity of the filter.

Photosensitive silicon chip having a ridge near an end photosite

In a photosensitive chip suitable for full-color imaging, separate photosites on the chip correspond to different primary colors in an original image. Each primary-color photosite is filtered with a polyimide doped to a particular primary color. The red-filtering layer and the blue-filtering layer are left on the non-photosensitive portions of the main surface of the chip, and together serve as a non-reflective area which prevents stray reflections from the chip. The chip is further provided with a base layer of infrared-filtering polyimide.

Filter architecture for a photosensitive chip

An assembly facilitates mounting a set of abutted semiconductor chips, such as chips aligned to form a single full-page-width linear array of photosensors in a digital scanner or copier. An elongated bead of electrically conductive adhesive extends along a surface of a support substrate. A plurality of semiconductor chips is disposed along the elongated bead, each semiconductor chip including a linear array of photosensors on a front surface thereof, and a back surface attached to the support substrate by the electrically conductive adhesive. A connection block is disposed along another portion of the elongated bead, the block including a first surface contacting the bead, a second surface, and a conductor extending from the first surface to the second surface.

Assembly for mounting semiconductor chips in a full-width-array image

In dicing of semiconductor chips from a wafer and mounting of the chips in an apparatus, techniques ensure the integrity of bonding pads and wire bonds in the dicing of individual chips and the connection of wire bonds to the chips. The wire bonds in the undiced chips are each connected to a probe pad disposed in an inter-chip area on the wafer, and this probe pad is used to accept probe pins which may otherwise damage the bonding pads on the chips themselves. In the dicing step, the probe pads are obliterated by the cutting blade. A polyimide dam disposes adjacent the bonding pads restricts the migration of liquid encapsulant securing the wire bonds to the bonding pads.

Semiconductor chip having a dam to prevent contamination of

A wafer design and dicing technique for creating semiconductor chips from wafers. A succession of oxide layers are deposited in first and second regions of a surface of a silicon substrate. The regions are separated by a street having no oxide layers therein, and the successive oxide layers form a vertical wall with a surface normal to the surface of the silicon substrate. A shock-absorbent material is deposited in the street, forming a concave meniscus therein. The shock-absorbent material retards the trajectories of silicon particles set into motion when the wafer is diced into chips.

Precision dicing of silicon chips from a wafer

An improved process for forming individual dies having faces that allow the dies to be assembled against other like dies to form one and/or two dimensional scanning arrays with minimal chipping and fracturing wherein the active side of a wafer is etched to form separation grooves with the wall of the grooves adjoining the die presenting a relatively wide surface to facilitate sawing, wide grooves are cut in the inactive side of the wafer opposite each separation grooves, and the wafer cut by sawing along the separation grooves, the saw being located so that the side of the saw blade facing the die is aligned with the midpoint of the wide wall so that on sawing the bottom half of the wall and the remainder of the grooves are obliterated leaving the top half of the wall to prevent cracking and chipping during sawing.

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Webster, NY, United States of America

Brian T Ormond