Motorola Corporation

Freescale Semiconductor,inc.

The University of Texas System

Brian T Kelley

David Mark Johnson

David B Taubenheim

Luis A Bonet

Jose G Corleto

Duncan M Fisher

Tan Nhat Dao

Satish S Kulkarni

Sekchin Chang

Jackseario Antonio Dionisio Do Rosario

Shareq Rahman

Various examples are provided for power quality of service optimization for microgrids. In one example, among others, a microgrid includes a smart meter configured to control supply of electric power to loads based at least in part upon energy consumption scheduling of the loads, which is based at least in part upon an effective electric generation capacity associated with the microgrid. The energy consumption scheduling can be based at least in part upon estimated power output of a sustainable energy resource of the microgrid and a load demand characterization of the loads. In another example, a system comprises a plurality of microgrids and an advanced metering infrastructure (AMI) configured to monitor operations of the microgrids and to control supply of electric power from sustainable energy resources and energy storage systems to loads of the microgrids via smart meters based at least in part upon energy consumption scheduling of the loads.

Power quality of service optimization for microgrids

Methods of recovering symbols and corresponding communication receivers including dual receivers configured to perform the method, where the method comprises: sampling a received signal that includes interference to provide received samples; determining a plurality of high power symbols and determining alternate symbols for a portion of the plurality of high power symbols based on the received samples and based on known training symbols; and deriving a sequence of recovered symbols corresponding to the received samples based on the received samples and augmented training symbols, the augmented training symbols comprising the known training symbols augmented by the plurality of high power symbols with one or more alternate symbols replacing a corresponding one or more high power symbols.

Recovering symbols in a communication receiver

A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom. In some embodiments of the invention, the virtual three-dimensional data representation comprises a plurality of segmented matrices, with the segmented matrices comprising data corresponding to portions of the incoming data frames. Data elements within the individual segments of the virtual three dimensional data structure can be calculated using data elements contained in a predetermined row and predetermined column of a segment.

Parallel processing for single antenna interference cancellation

A frequency offset estimator () and corresponding method () provides a frequency offset estimate () for an OFDM signal. The estimator comprises a data parser () coupled to an input signal () and arranged to select a group of symbols (-) or corresponding samples corresponding to predetermined symbols from the input signal and a processor () arranged to provide a correlation corresponding to the symbols, where the correlation corresponds to a frequency offset estimation for the input signal and is determined in a sequential fashion so that the correlation is provided concurrently with the last symbol or sample of the group of symbols to be selected.

OFDM frequency offset estimation apparatus and method

A decorrelating rake receiver () using a signal processor () and corresponding method () to determine filter coefficients (). The decorrelating rake receiver includes a plurality of filters () arranged to be coupled to an input signal () and the filter coefficients (), the plurality of filters operable to provide a plurality of output signals and a coefficient generator (), coupled to the input signal, to explicitly and definitely determine the filter coefficients for the plurality of filters such that the plurality of filters perform a decorrelating rake process. The decorrelating rake receiver further includes a combiner () to combine the plurality of output signals and provide a received signal (). The decorrelating rake receiver () is suitable for use in a wireless communication device () or base transceiver ().

Decorrelating rake receiver apparatus and method

Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.

Reconfigurable vector-FFT/IFFT, vector-multiplier/divider

A mixer (,) including a transformation circuit (,) is used for frequency converting a first digital signal (,), sampled at a first sampling rate and operating at a first frequency, to a second digital signal (,) operating at a desired frequency. The transformation circuit (,) is adapted to modify and filter the first digital signal (,) to eliminate unwanted frequencies in the first digital signal (,) and to alter the first sampling rate of the first digital signal (,) by a predetermined factor to generate a modified and filtered first digital signal (,) operating at a second sampling rate and the first frequency. The transformation circuit (,) is further adapted to mix the modified and filtered first digital signal (,) with a predetermined injection signal (,) to generate the second digital signal (,) operating at the desired frequency and the second sampling rate.

Method and apparatus for mixing signals

A radio receiver circuit (,) is used for receiving a multi-level signal (,) that includes a plurality of symbols, wherein each level is representative of a symbol of data. Baseband samples are generated for each symbol, whereby each baseband sample has a phase and a signal level. The radio receiver circuit (,) measures the received signal environment. A digital circuit (,) selects a scan duration from a scan duration table (,) based on the measured signal environment and a combination of signal types used for classification of the received signal. The digital circuit tallies, by category, occurrences of the baseband samples, whereby each category is representative of one of a plurality of phases, and one of a plurality of signal level ranges. The digital circuit (,) selects a set of optimized thresholds from a table of predetermined, optimized thresholds (,), based on the measured signal environment and a combination of signal types, and correlates the tallies to at least one template, and classifies the multi-level signal according to the correlation results and the selected optimized thresholds.

Method and apparatus for adaptively classifying a multi-level signal

An automatic frequency control circuit (,) and a method for automatic frequency control in a digital receiver includes a CORDIC vector rotation processor (,), an FM demodulator (,) and an integrator (,). The circuit and method utilize the CORDIC computing technique to simplify required circuitry and to reduce required software processing power over conventional automatic frequency control techniques.

Electronic circuit and method for automatic frequency control

A multiply accumulate circuit (600) includes a multiply accumulate reduction circuit (527) that generates P current accumulated operands during an iteration. P operand registers (582) are coupled to the multiply accumulate reduction circuit (527). A corresponding one of the P current accumulated operands is stored in each of the P operand registers (582) in place of one of the P partial accumulated operands in response to the iteration. Each of P feedback paths (593) couples one of P outputs of the P operand registers (582) to a corresponding one of P feedback inputs of the multiply accumulate reduction circuit (527). An adder (561) that is coupled to the P outputs through isolation circuits (570) generates an output (551) in N iterations that is a sum of N products, each being a product of one of a series of N multipliers and one of a series of N multiplicands.

Multiply and accumulate circuit

A digital signal processor having a multiplierless computation block (140) is accomplished by storing approximations of computed logarithms in memory (160, 162). When two pieces of data (114, 116) are received, the approximate logarithms, or logarithmic data (120, 128), for each of the pieces data are retrieved from memory. The logarithmic data (120, 128) is them summed to produce a resultant (136), wherein the resultant (136) is used to retrieve an inverse logarithmic approximation (180) that is stored in memory (170, 172) in a manner similar to that of the logarithmic approximations. The inverse logarithmic approximation (180) that results closely approximates the product of multiplying, or another arithmetic function, the two pieces of data (114, 116).

Method and apparatus for a digital signal processor having a

A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).

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Austin, TX, United States of America

Brian T Kelley