Gte Laboratories Incorporated

Brian T Devlin

Emel S Bulat

In fabricating a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is marked in a pattern to expose a plurality of elongated surface areas. The wafer is subjected to reactive ion etchings in SiCl.sub.4 and Cl.sub.2 and subsequently in Cl.sub.2 to form parallel grooves with rounded intersection between the wide walls and bottoms of the grooves. Ridges of silicon are interposed between grooves. A layer of silicon oxide is grown on all the silicon surfaces. The grooves are filled with deposited silicon oxide and silicon oxide is removed to form a planar surface with the upper surfaces of the ridges. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves, N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, source ridges, and the bottom of the substrate.

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Haverhill, MA, United States of America

Brian T Devlin