Texas Instruments Corporation

Other

Stmicroelectronics Gmbh

Brian T Deng

Philip A Roden

William Alan Saperstein

Dinghui Richard Nie

Merril Ray Newman

Khodor S Elnashar

Clarence D Lewis

Joseph Michael Erickson

Stephen Li

Matthew J DiMarco

Steve K Tsang

Mahmoud M Yazdani

Jian Yu

Henry N Angulo

Bob Gugel

Fengchun Duan

Michael D McKinney

David E Kimble

An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.

Electronic device for communicating between a microcontroller unit (MCU) and a host processor and related methods

A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time slot for the transmission of one data packet from a selected one of the plurality of data queues. There is one arbitration logic circuit for each of the plurality of entries in the arbitration table. Each arbitration logic circuit includes a first multiplexer receiving an output from a first table entry and an output from a second table entry in the arbitration table. A second multiplexer receives empty flags from each of the data queues, the flags indicating that there is no data to the sent from that queue. An output of the second multiplexer is coupled to a control input of the first multiplexer so that the first table entry value is output from the first multiplexer if the corresponding queue has data to be sent out and the second table entry value is sent out from the first multiplexer if the queue corresponding to that table entry has data to be sent out and the queue corresponding to the first entry has no data to be sent out.

Weighted round-robin arbitrator

A bridge controller controls the data flow to/from a USB bus to/from an ATA/ATAPI drive, such as an ATA hard drive or ATAPI CD or DVD drive. The bridge controller has a state machine which receives the CBW in a background mode in real time as the packet is being transferred to the bridge controller. The state machine uses the CBW to set up the data transfer. The bridge controller also has a programmable processor which is coupled to the CBW once it is received in a buffer memory. The programmable processor makes changes in the set up of the receiving device for the transfer, if needed, and initiates the data transfer.

High speed bridge controller adaptable to non-standard device configuration

Apparatus and method for microcontroller debugging. A preferred embodiment microcontroller integrated circuit comprises debug circuitry on the integrated circuit. The debug circuitry is capable of breaking normal instruction execution based on an address breakpoint, a stack pointer breakpoint, or a single step breakpoint. Upon detection of a valid breakpoint, the debug circuitry substitutes a jump to a debug program instruction in place of the next normal application program instruction. The debug program then may provide microcontroller status to a developer, allowing the developer to debug the application program. Upon completion of the debug program, control of the microcontroller is returned to the application program at the point of interruption.

Apparatus and method for microcontroller debugging

A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.

ATAPI device unaligned and aligned parallel I/O data transfer controller

A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different clocks to handshake in the background, thereby reducing bus idle time.

Bus transaction accelerator for multi-clock systems

A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis. A priority encoder unit is included for receiving the interrupt requests stored in the storage units and providing the interrupt requests as outputs for processing by the microprocessor, on a priority basis.

Priority first come first serve interrupt controller

A post write buffer for a dual clock system which improves the utilization of host data bus ( ) bandwidth is provided which consists of an address buffer ( ), a data buffer ( ), a first clock timing signal ( ), a second clock timing signal ( ), an address decoder ( ), a first write enable circuit ( ), and a second write enable circuit ( ). The address-buffer ( ) and data buffer ( ). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder ( ) determines which destination register byte will receive the data in the host data bus ( ). The write enable circuits ( ) synchronize the clock signals ( ) and determine when the destination register is ready to receive the data from the data buffer ( ).

Post write buffer for a dual clock system

An improved counter register ( ) and method of transferring data from a host data bus ( ) controlled by a first clock source (BCLK) to the cycle timer ( ) controlled by a second clock source (NCLK) which frees the host data bus ( ) to perform other functions while a clock synchronization process occurs to allow the data ( ) to be written to the counter register ( ) or read from the counter register ( ). This synchronization scheme is such that at any time the host data bus ( ) may read data ( ) from the cycle timer ( ) and retrieve the current counter register value. In the alternative, at any time, the host data bus ( ) may write to the cycle timer ( ) and it will receive this data ( ) immediately. In either case, the data is transferred immediately without the host data bus ( ) having to wait for synchronization across the aforementioned clock boundary.

Counter register monitor and update circuit for dual-clock system

A method for reading data from an IEEE 1394 serial bus system and storing the data in a FIFO includes partitioning the FIFO into a plurality of registers, each having 32 register bits for the data and a single register bit for a control data bit. To manipulate the system such that reads on a data quadlet involve only one system read on a 32-bit system, a packet token is stored in the initial register in a data packet. This packet token includes the quadlet count in the data packet. The host system need only read the first register in the data packet, the packet token, to determine the number of data quadlets within the data packet. Thereafter, the control data bit need not be read such that only a single read operation is performed for each operation of the read pointer. The last register associated with the packet is the acknowledge register which contains information that is sent back to the transmit node in the system. Further, each data packet can be divided into partitions with a plurality of packet tokens. Each packet token has a defined quadlet count associated therewith, the packet tokens disposed at the beginning of each partition. The last partition has a Complete bit set equal to &ldquo;1&rdquo; to define that as a the last partition. In this last packet token, the acknowledge signal is stored.

Method and apparatus for buffering received data from a serial bus

An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).

Apparatus and method for processing packetized information over a serial

The invention comprises a method and system for testing memory in an interface system 10 coupling a parallel host bus 30 to a serial bus 20. The system comprises a random access memory 70 having a plurality of memory locations for temporarily storing data received from either the parallel host bus 30 or the IEEE 1394 serial bus 20, the random access memory 70 being logically divided into a transmit memory portion and a receive memory portion. The interface also comprises a transmission control unit 40 operable to control transmission of data from the parallel host bus 30 to the IEEE 1394 serial bus 20. The transmission control unit 40 is further operable to access the transmit memory portion of the random access memory 70. The interface also comprises a reception control unit 50 operable to control reception of data by the parallel bus 30 from the serial bus 20. The receive control unit 50 is further operable to access the receive memory portion of the random access memory 70. The interface further comprises a test unit 60 operable to selectively obtain control of the random access memory 70 based on a control signal received from the parallel host bus 30; internally generate addresses for each memory location within the random access memory 70; control transmission of parallel data from each memory location associated with the internally generated addresses to the parallel host bus 30 for inspection; and selectively relinquish control of the random access memory 70 to allow transmission of data between the IEEE 1394 serial bus 20 and the parallel host bus 30.

Method and system for testing memory

A block data transfer system may comprise a microprocessor integrated within a bus controller, a bus, and a plurality of computer boards coupled together via the bus. A (programmable array logic device), integrated within the bus controller, allows an efficient block transfer of data between components on the computer boards by asserting a binary signal to indicate to the bus controller when to continue the data transfer and when to truncate the data transfer. The utilizes a counter, dependent upon the data transfer size, to control the binary indication signal. The binary signal overrides the architectural data transfer protocol, thereby eliminating 'protocol overhead' timing associated in multiple data transfers by allowing the entire data block to transfer within one transfer protocol period.

Multiple block transfer mechanism

A method and apparatus for a circuit physically realizing a Universal Asynchronous Receive/Transmit (UART) circuit 31, 40 having an automatic flow control feature. A preferred embodiment includes a UART 31 provided with additional control circuitry 39, 34 for automatically pausing transfers from the transmit data circuitry 35, 32 in response to a transition at the CTS (Clear to Send) input, and further provided with control circuitry 39 for automatically asserting and deasserting a RTS (Ready to Send) output when a receiver data threshold is reached.

Universal asynchronous receive/transmit circuit with flow control

A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and 'live-lock' conditions.

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Richardson, TX, United States of America

Brian T Deng