Fairchild Semiconductor Corporation

Fairfield Semiconductor Corporation

Brian Sze-Ki Mo

Izak Bencuya

Duc Q Chau

Dean E Probst

Steven Paul Sapp

Ashok Challa

A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.

FET device having ultra-low on-resistance and low gate charge

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Method of manufacture and structure for a trench transistor having a heavy body region

In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

Method of forming a FET having ultra-low on-resistance and low gate charge

Method of manufacturing a trench transistor having a heavy body region

A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100&#xb0; C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

Method of forming a trench transistor having a superior gate dielectric

Field effect transistor and method of its manufacture

A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.

Vertical MOSFET with ultra-low resistance and low gate charge

A trench field-effect transistor with a self-aligned source. At least a portion of the source implantation dose ( ) is implanted underneath the gate ( ) of a trench transistor by implanting an a non-orthogonal angle to the sidewall ( ) of the trench. In one embodiment, a slow diffuser, such as arsenic, is implanted to minimize the post-implant diffusion. The resulting structure ensures gate-source overlap, and a consistent, small, gate-source capacitance with a lower thermal budget for the resultant device. The narrow depth of the source, in conjunction with its unique L-shape, improves device ruggedness because the source doping does not compensate the heavy body doping as much as with conventional devices. In one embodiment, the substrate is rotated 90 degrees within the implanter to implant both sidewalls of a trench.

Trench transistor with self-aligned source

A method of manufacturing a trenched field effect transistor that includes a heavy body structure. The method includes forming a plurality of trenches into a semiconductor substrate having dopants of a first conductivity type, wherein the gate electrode of the transistor is formed. A doped well having dopants of a second conductivity type is formed into the substrate and between the trenches. Source regions having dopants of the first conductivity type are formed inside the doped well adjacent to and on opposite sides of the trenches. A heavy body region having dopants of the second conductivity type is formed inside each doped well and at a depth that is shallower than the doped well. The heavy body is formed in a manner that makes an abrupt junction between the heavy body and the well. In one embodiment, the abrupt junction is formed by a dobule implant process.

Method of manufacturing a field effect transistor

A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100&deg; C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

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Fremont, CA, United States of America

Brian Sze-Ki Mo