Intel Corporation

Brian S Morris

Robert G Blankenship

Debendra Das Sharma

Michelle C Jen

Bill Nale

Sreenivas Mandava

John H Crawford

Binata Bhattacharyya

Mohan J Kumar

Rajat Agarwal

Raghunandan Makaram

Kenneth C Creta

Vedaraman Geetha

Jeffrey Charles Swanson

Debaleena Das

Suneeta Sah

Balint Fleischer

Massimo Sutera

Eric L Hendrickson

Francis X Mckeen

Raj K Ramanujan

Simon P Johnson

Utkarsh Y Kakaiya

George Zacharias Chrysos

Joshua David Fender

Pratik M Marolia

Amy L Santoni

Mohan Nair

Suresh S Chittor

Henk G Neefs

Roy M Stevens

Andrew Yang

Krishnakumar Nair

Mathew W Stefaniw

Ted Rossin

Kuljit Singh Bains

Siddhartha Chhabra

Yen-Cheng Liu

James K Pickett

Dennis Ryan Bradford

Sailesh Kottapalli

Bruce Querbach

Dong Wang

Brian J Hickmann

Jeff Willey

Woojong Han

Mohamed Arafa

Mani Prakash

John K Grooms

Michael Rotzin

Edward L Payton

Maciej Urbanski

George H Huang

A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Sharing memory and I/O services between nodes

Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

Securely exposing an accelerator to privileged system components

A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

Shared buffered memory routing

Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a corresponding product, shift the corresponding products with a set of shift registers based on a maximum exponent of exponents for the corresponding products determined by a maximum exponent determiner to produce shifted products, perform an numeric conversion operation on the shifted products with a set of numeric conversion circuits based on sign bits from the same element position of the first floating-point vector and the second floating-point vector to produce signed representations of the shifted products, add the signed representations of the shifted products with a set of adders to produce a single product, and normalize the single product with a normalization circuit based on the maximum exponent into a single floating-point resultant, and in the second mode, each multiplier of the set of multipliers is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product with the set of adders to produce a single integer resultant.

Apparatuses and methods to accelerate matrix multiplication

A deck fasteners alignment tool enables accurate positioning of deck boards before being fastened to respective deck joists. The alignment tool includes or defines a pair of V-shaped recesses on a template body which provides proper alignment to deck fasteners so long as outer locating pins are aligned with laterally adjacent gaps between deck boards, respectively. The alignment tool includes a pair of internally positioned neodymium magnets adjacent the alignment recesses for magnetically holding deck board screws in a perpendicular or upstanding position so that the screws may be driven single-handedly by the person building the deck. In addition, some embodiments provide the alignment tool with laterally adjustable V-shaped recesses for selectively aligning deck fasteners into laterally adjacent ribs of the deck boards, respectively.

Deck fasteners alignment tool

Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.

Artificial neural network training using flexible floating point tensors

A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

Supporting configurable security levels for memory address ranges

Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

Method and apparatus for partial cache line sparing

Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

Error handling in transactional buffered memory

A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

Early identification in transactional buffered memory

Growing community of inventors

Santa Clara, CA, United States of America

Brian S Morris