Rambus Inc.

Apple Inc.

Brian S Leibowitz

Jared L Zerbe

Hae-Chang Lee

Jihong Ren

Frederick Abbott Ware

Akash Bansal

Qi Lin

Jaeha Kim

Jafar Savoj

Kyung Suk Oh

Jade M Kizer

John M Wilson

Lei Luo

John Wood Poulton

Kevin S Donnelly

Fred F Chen

Masum Hossain

Ramin Farjad-Rad

Ely K Tsern

Yohan Usthavia Frans

Nhat M Nguyen

Fariborz Assaderaghi

Simon Li

Ian P Shaeffer

Wayne S Richardson

Lawrence Lai

Fan Ho

David A Secker

Andrew P Ho

Thomas Hastings Greer

John Cronan Eble, Iii

Wayne D Dettloff

Ruwan Ratnayake

Sanjay Pant

Barry William Daly

Emerson S Fang

Sanjeev K Maheshwari

Thomas H Greer, Iii

Teva J Stone

Marko Aleksić

Hsuan-Jung Su

Mark A Horowitz

Wayne Frederick Ellis

Amir Amirkhany

Kishore Ven Kasamsetty

Pradeep Batra

John Welsford Brooks

Marko Aleksic

Ryan D Bartling

Vladimir Marko Stojanovic

Huy M Nguyen

Jose A Tierno

Trung Am Diep

Andrew C Ho

Chaofeng Huang

Michael D Bucher

Hsuan-Jung (Bruce) Su

Bruno Werner Garlepp

Pradeep R Trivedi

Bo Sun

Gin S Yee

Praveen R Singh

Kun-Yung Chang

Michael R Seningen

Mohamed Hassan Abu-Rahma

Farshid Aryanfar

Dinesh D Patil

Pravin Kumar Venkatesan

Reza Navid

Jie Shen

Chintan S Thakkar

Shah M Sharif

Haechang Lee

Haiming Jin

Anshuman Bhuyan

WooPoung Kim

Thomas H Iii Greer

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

High-speed signaling systems with adaptable pre-emphasis and equalization

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Interface with variable data rate

An integrated circuit (IC) chip includes transfer circuitry to transfer signals between the IC chip and a second IC chip. The transfer circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate a respective tap weight for each of the at least one tap based on edge information of previously transferred signals.

Edge based partial response equalization

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

High-speed signaling systems and methods with adaptable, continuous-time equalization

A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

Hybrid serial receiver circuit

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Memory device comprising programmable command-and-address and/or data interfaces

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Data transmission using delayed timing signals

To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.

Serial data receiver circuit with dither assisted equalization

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

Self referenced single-ended chip to chip communication

Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Detecting power supply noise events and initiating corrective action

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

Latency reduction in analog-to-digital converter-based receiver circuits

Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.

On-chip supply ripple tolerant clock distribution

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San Francisco, CA, United States of America

Brian S Leibowitz