Infineon Technologies Ag

International Business Machines Corporation

Other

Infineon Technologies North America Corp.

Brian S Lee

Helmut Horst Tews

Ulrike Gruening

Rajarao Jammy

Johnathan E Faltermeier

Stephan Kudelka

Uwe Paul Schroeder

Suryanarayan G Hegde

Alexander Michaelis

Till Schlösser

Beth Ann Peterson

Dale Francis Riedy, Jr

Susan Kay Candelaria

Byeong Yeol Kim

Heon Lee

John Richard Paveza

Gangadhara Swami Mathad

Munir D Naeem

Rajiv M Ranade

Chung Man Fung

Joachim Hoepfner

Young-Jin Park

Ronald E Bretschneider

Raj Jammy

John Faltermeier

Elizabeth Morales

Stephan P Kudelka

Write transfer resource management in a data storage system in accordance with the present description includes overdue write transfer management logic which detects whether or not an established write set has become stale. In one embodiment, a determination is made as a function of whether a write transfer from a host and associated with an established write transfer set is overdue as measured by a time-out period of time. Upon determination that an established write transfer set has become stale, the stale write set is removed and the resources associated with the removed write set are freed for use by other write sets, significantly improving system performance. Other features and aspects may be realized, depending upon the particular application.

Write transfer resource management in a data storage system

The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

DRAM cell arrangement with vertical MOS transistors

DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

DRAM cell arrangement with vertical MOS transistors, and method for its fabrication

Plasma doping for DRAM with deep trenches and hemispherical grains

A system and method of forming an electrical connection ( ) to the interior of a deep trench ( ) in an integrated circuit utilizing a low-angle dopant implantation ( ) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate ( ) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material ( ) overlying or in the trench, leaving a self-aligned mask ( ) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

Method of forming a vertically oriented device in an integrated circuit

Control of oxide thickness in vertical transistor structures

A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.

Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates

A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a < > crystal plane and a < > crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the < > crystal plane of the trench side wall, but not into the < > crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Process for fabricating a uniform gate oxide of a vertical transistor

A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar ) is protected by a mask (e.g., polysilicon ), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall ( ) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide ) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Integrated circuit vertical trench device and method of forming thereof

A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures.

Method of reducing RIE lag for deep trench silicon etching

In accordance with the invention, a method for opening holes for semiconductor fabrication includes the steps of providing a pad stack on a substrate, forming a hard mask layer on the pad stack, the hard mask layer selectively removable relative to the pad stack, patterning a resist layer on the hard mask layer, the resist layer being selectively removable relative to the hard mask layer and having a thickness sufficient to prevent scalloping, etching the hard mask layer selective to the resist layer down to the pad stack, removing the resist layer. After removing the resist layer, the pad stack is etched selective to the hard mask layer such that a hole is opened down to the substrate.

Differential trench open process

A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a &lt;100&gt; crystal plane and a &lt;110&gt; crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the &lt;110&gt; crystal plane of the trench side wall, but not into the &lt;100&gt; crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

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New York, NY, United States of America

Brian S Lee