Promos Technologies, Inc

Brian S Lee

John Walsh

Chih-Yu Lee

An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180&#xb0; phase difference from second regions with 0&#xb0; phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same

A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices

An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180&deg; phase difference from second regions with 0&deg; phase difference to define active areas or gate-lines in a DRAM chip.

Method for fabricating semiconductor device with loop line pattern structure

The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si Ge (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Semiconductor device with SI-GE layer-containing low resistance, tunable contact

An improved buried strap method in the fabrication of a DRAM integrated circuit device is described. A deep trench is etched into a substrate. A collar is formed on an upper portion of the deep trench. A buried plate is formed by doping around a lower portion of the deep trench and a capacitor dielectric layer is formed within the deep trench. The deep trench is filled with a silicon layer wherein the silicon layer forms a deep trench capacitor and covers the collar. The silicon layer is recessed below a top surface of the substrate to leave a recess. A top portion of the collar is etched away to leave a collar divot. A hemispherical grain polysilicon layer is selectively deposited into the deep trench and filling the collar divot. The HSG layer is doped in-situ or by post plasma doping. The doped hemispherical grain polysilicon layer forms a buried strap in the fabrication of a deep trench DRAM integrated circuit device.

Buried strap formation method for sub-150 nm best DRAM devices

A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Method of forming a deep trench DRAM cell

The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and diffusion barrier layer. Thus, no additional glue layer or diffusion barrier layer needs to be formed. Moreover, the metal contact of the present invention can be integrated with a DRAM by a hybrid contact method. Implantation contact is used in pFET regions and diffusion contact is used in nFET regions. This can reduce mask steps and production costs.

Semiconductor device having contact of Si-Ge combined with cobalt silicide

A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer. The bit line contact openings, substrate contact openings, and gate contact openings are filled with a conducting layer to complete formation of contacts in the fabrication of a DRAM integrated circuit device.

Consolidation method of junction contact etch for below 150 nanometer deep trench-based DRAM devices

An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (R ), with ultra-shallow contact junction depth (X ) and high doping concentration in the silicide contact interface (N ).

Advanced contact integration scheme for deep-sub-150 nm devices

An improved buried strap method in the fabrication of a DRAM integrated circuit device where the active area is self-aligned to the deep trench in the length direction only is described. An etch stop layer is provided on a substrate. A deep trench is etched into the substrate not covered by the etch stop layer and filled with a silicon layer to form a deep trench capacitor. A polysilicon layer is deposited over the capacitor to form a buried strap. A liner layer is deposited over the etch stop layer and the buried strap having the same material as the etch stop layer. A hard mask material is deposited over the liner layer and etched where it is not covered by a mask wherein etching stops at the liner layer. The liner layer and the etch stop layer are etched away where they are not covered by the hard mask layer to form an etch stop frame. The substrate and the deep trench are etched into where they are exposed by the hard mask and the etch stop frame to form isolation trenches. The isolation trenches are filled with a dielectric layer. Gate electrodes are formed overlying the isolation trenches and the substrate. The substrate is annealed whereby dopants from the buried strap diffuse into the substrate to form a buried strap diffusion wherein the buried strap diffusion connects the deep trench capacitor to one of the gate electrodes to complete the buried strap DT DRAM device.

Self-aligned active array along the length direction to form un-biased buried strap formation for sub-150 NM BEST DRAM devices

Semiconductor device with Si-Ge layer-containing low resistance, tunable contact

An improved etch sequence and an improved integration scheme of plasma doping in the fabrication of a DRAM integrated circuit device are described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an array area and a periphery area. The semiconductor device structures are covered with a dielectric layer. The dielectric layer is concurrently etched through in the array area to form bit line contact openings and in the periphery area to form substrate contact openings. Doped regions are formed in the substrate exposed within the bit line contact openings and the substrate contact openings using a plasma doping process. Next, the dielectric layer is etched through to form a gate contact opening. Thereafter, the bit line contact openings, the substrate contact openings, and the gate contact opening are filled with a conducting layer to complete forming contacts in the fabrication of a DRAM integrated circuit.

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Hsinchu, Taiwan

Brian S Lee