Hewlett Packard Enterprise Development LP

Brian S Birk

Gregg Bernard Lesartre

Craig William Warner

Harvey Ray

Martin Foltin

Chris Michael Brueggen

Joseph F Orth

Robert R Imark

Examples described herein relate to method for measuring a disconnect response time. The method includes discontinuing, in response to a determining that a disconnect response metric test is to be initiated, transmission of a test optical signal by a test device to a DUT coupled to the test device, wherein the DUT is to discontinue transmission of a response optical signal to the test device upon detection of a loss of the test optical signal. Further, a loss of the response optical signal by may be detected by the test device. Furthermore, a disconnect response metric of the DUT may be determined by the test device based on a time of discontinuation of the transmission of the test optical signal and a time of detection of the loss of the response optical signal.

Determination of a disconnect response metric for an optical device

In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

Write tracking for memories

In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

Error correction code in memory

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Corvallis, OR, United States of America

Brian S Birk