Texas Instruments Corporation

Brian Roger Elies

Steven Craig Bartling

Sudhanshu Khanna

Abhijit Kumar Das

Wei-Yan Shih

Krishnasawamy Nagaraj

Michael Zwerg

An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

Methods and apparatus to improve differential non-linearity in digital to analog converters

A circuit includes a transistor input pair, a differential input having a comparator input, and a level shifter. The transistor input pair is adapted to be coupled between a voltage supply and a comparator output. The transistor input pair includes a first transistor having a gate and a drain. The drain of the first transistor is coupled to the comparator output. The level shifter is coupled between the transistor input pair and the differential input. The level shifter includes a second transistor having a gate and a source. The gate of the second transistor is coupled to the comparator input. The source of the second transistor is coupled to the gate of the first transistor.

Comparator architecture supporting lower oxide breakdown voltages

In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

Piezo-electric sensor reset

In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

High-voltage switches

An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.

Differential sensor using thin-film piezoelectric capacitors

An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.

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Frisco, TX, United States of America

Brian Roger Elies