International Business Machines Corporation

Brian Robert Prasky

James J Bonanno

Chung-Lung K Shum

Steven R Carlough

Fadi Y Busaba

Christopher A Krygowski

Anthony Saporito

Adam B Collura

Vijayalakshmi Srinivasan

Daniel Lipetz

Eric M Schwarz

Jonathan D Bradbury

Khary J Alexander

Alper Buyuktosunoglu

Ulrich Mayer

Christian Jacobi

Brian William Curran

Edward Thomas Malley

Michael J Cadigan, Jr

Charles Franklin Webb

David S Hutton

Allan Mark Hartstein

Thomas R Puzak

Matthias D Heizmann

Philip George Emma

Robert J Sonnelitter, Iii

Gregory William Alexander

Aaron Tsai

John G Rell, Jr

Bulent Abali

Harold Wade Cain, Iii

Martin Recktenwald

Deanna Postles Dunn Berger

David Michael Daly

Joshua M Weinberg

Brian William Thompto

Jonathan T Hsieh

James R Mitchell

James Raymond Cuffney

Moinuddin Khalil Ahmed Qureshi

Timothy John Slegel

Eli M Dow

Marcel Mitran

James Paul Gilchrist

John-David Wellman

Barry Watson Krumm

Willm Hinrichs

Jang-Soo Lee

Richard John Moore

Steven J Hnatko

Akash V Giri

Keith N Langston

Alexander A Vasilevskiy

Dominic Ditomaso

Andrew Dow

Katrin Nagel

Nickalaus A Painter

Suman Amugothu

Gabriel J Perez Irizarry

Gary S Littlefield

Joran Siu

Lisa Cranton Heller

William Vincent Huott

K Paul Muller

Natesan Venkateswaran

Mark Anthony Check

Rolf Sautter

Frank Siegfried Lehnert

Ashutosh Misra

Norbert Hagspiel

John Stephen Liptay

David Andrew Schroter

Michael Billeci

John Wesley Ward, Iii

Eyal Naor

Richard Frank Rizzolo

Marie S Cole

Richard Esten Bohn

Yair Fried

Deepankar Bhattacharjee

Jayapreetha Natesan

James Philip O'Connor

Douglas Alexander Smalley

Varnika Atmakuri

Moinuddin K A Qureshi

Charles E Vitu

Nidhi Nijhawan

Sierra R F Spring

Chunming Lin

Corey C Stappenbeck

Ioana Monica Burcea

Chung-Iung K Shum

Linda M Bigelow

A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.

Branch prediction using speculative indexing and intraline count

A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

Cache line compression prediction and adaptive compression

Embodiments include a hierarchical metadata prediction system that includes a first line-based predictor having a first line for storage of metadata entries, and a second line-based predictor configured to store metadata entries from the first line-based predictor. The second line-based predictor has a second line, the second line including a plurality of containers, the plurality of containers including at least a first set of containers having a first size and a second set of containers having a second size. The system also includes a processing device configured to transfer one or more metadata entries between the first line-based predictor and the second-line based predictor. Embodiments also include a computer-implemented method and a computer program product.

Variable formatting of branch target buffer

Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.

Metadata predictor

Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of prescribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of prescribed manners.

Updating metadata prediction tables using a reprediction pipeline

Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Computation and placement of error correcting codes (ECC) in a computing system data cache

A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.

Multi purpose server cache directory

Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.

Using metadata presence information to determine when to access a higher-level metadata table

Embodiments include storing return addresses for a branch-target-buffer. Aspects include receiving a first instruction and based on a determination that the first instruction is a branch instruction and potentially a call, storing a return address associated with the branch instruction in a prediction return address table, wherein the prediction return address table includes an entry that corresponds to an index value that is created based on a target address of the first instruction, and wherein the entry includes the return address that is created based on an address of a sequential instruction of the first instruction. Aspects also include receiving a second instruction and based on a determination that the second instruction is predicted to be a return instruction with a predicted return address table index value from the branch-target-buffer, using the index value to select the return address to predict as the target address.

Return address table branch predictor

Low latency in a non-uniform cache access ('NUCA') cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.

Transparent interleaving of compressed cache lines

Embodiments are provided for an integrated semi-inclusive hierarchical metadata predictor. A hit in a second-level structure is determined, the hit being associated with a line of metadata in the second-level structure. Responsive to determining that a victim line of metadata in a first-level structure meets at least one condition, the victim line of metadata is stored in the second-level structure. The line of metadata from the second-level structure is stored in a first-level structure to be utilized to facilitate performance of a processor, the line of metadata from the second-level structure including entries for a plurality of instructions.

Integrated semi-inclusive hierarchical metadata predictor

A method, system, and computer program product algorithmically analyzes scoring data from a competitive event where the scoring, determined by a plurality of evaluators, is based on subjective criteria. The method receives, and/or determines a scale factor associated with each evaluator. The method adjusts scores awarded by each evaluator, based on respectively corresponding scale factors, to arrive at normalized scores. The method, thereby minimizes influences of biases associated with the evaluators.

Detecting and removing bias in subjective judging

A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.

Skip-over offset branch prediction

A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.

Hierarchical metadata predictor with periodic updates

A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.

Call/return stack branch target predictor to multiple next sequential instruction addresses

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Wappingers Falls, NY, United States of America

Brian Robert Prasky